From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C867C2D3A91; Tue, 15 Jul 2025 03:43:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551018; cv=none; b=bJ7CECHTs/c5sP3SQNz+U+ElyS0b9vxjbPq/kBrRDQcGyTewkhmtovVKDPRPNLTqqspA2zptrPIXpeDUatmaiquyJR1+Wc5JtkLFbF6BzZgiU8VLIk2LDuQy1XximtBcU2Q5rYeljlPP0pZg9aDtTRa4kjoUGnwzAoIX4DU8/oA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551018; c=relaxed/simple; bh=RqjotwS+RxLBGQqfKYO247rq44b0pwn5qtigHjVvh8k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ru8gXMv/mHRnXJ3vctzhVYHkfYM+wW0Q/cBe758Ig2IxqDVtRAmd7UDj1a6LnGa3Q12ULbVPHzUuMJ++oaz0Z4ZjD5FZax0uLeBXCaiWmYrmPTAlcvPQrbgoPet1sEA6IRLI8MVQ0VrwAD3d7BtxYILGqy6rMsSeVhR8EtbrmFc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Date: Tue, 15 Jul 2025 11:43:15 +0800 Message-ID: <20250715034320.2553837-6-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Add pinctrl support for PCIe RC PERST#. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi index 289668f051eb..ea879f086c25 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -2,6 +2,11 @@ // Copyright 2019 IBM Corp. &pinctrl { + pinctrl_pcierc1_default: pcierc1-default { + function = "PCIERC1"; + groups = "PCIERC1"; + }; + pinctrl_adc0_default: adc0_default { function = "ADC0"; groups = "ADC0"; -- 2.43.0