From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 890152D46C8; Tue, 15 Jul 2025 03:43:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551020; cv=none; b=KrzvPeDR4RgGs6WB+YtcfkvVCJJYrepuwFiYBv0C7tGv4x3bgtkp0ZhufOf84riaSuB3pQjAJzKA7H7CDW9gwKa/lpBeAyKKOtLbiHVOjqlju/YKOp2hptGEiaJSfJSDgVNCZRvFQ7aCyQuSCZGcAB13gNb2CnsdF07E0Vi0Msg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752551020; c=relaxed/simple; bh=hjViZpXEUkSxf617dnE/GzfBvxIbI8+B9htFKuVtR24=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pNwI8knqKbzyFRUkT4tvmV92B0aafln4By7Jg4mlnvqRmCxRaZTU5940IVNAPbZn1TXLLg+EDGvjFF+nEIxsGBZO8aaRaD4kDeoHA7QoeCvGj7VVeEqWDqlDfaugYxL/X0JU3rCw0uBbmOUUcgLWerNhiMzP2Mq4P0WRz+g1V8E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 15 Jul 2025 11:43:21 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 15 Jul 2025 11:43:21 +0800 From: Jacky Chou To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node Date: Tue, 15 Jul 2025 11:43:16 +0800 Message-ID: <20250715034320.2553837-7-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> References: <20250715034320.2553837-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The AST2600 has one PCIe RC, and add the relative configure regmap. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 61 +++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 8ed715bd53aa..ed99780b6860 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -379,6 +379,67 @@ rng: hwrng@1e6e2524 { quality = <100>; }; + pcie_phy1: syscon@1e6ed200 { + compatible = "aspeed,pcie-phy", "syscon"; + reg = <0x1e6ed200 0x100>; + }; + + pcie_cfg: syscon@1e770000 { + compatible = "aspeed,pcie-cfg", "syscon"; + reg = <0x1e770000 0x80>; + }; + + pcie0: pcie@1e7700c0 { + compatible = "aspeed,ast2600-pcie"; + device_type = "pci"; + reg = <0x1e7700c0 0x40>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x80 0xff>; + + ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 + 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; + + status = "disabled"; + + resets = <&syscon ASPEED_RESET_H2X>; + reset-names = "h2x"; + + #interrupt-cells = <1>; + msi-parent = <&pcie0>; + msi-controller; + + aspeed,ahbc = <&ahbc>; + aspeed,pciecfg = <&pcie_cfg>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + pcie@8,0 { + reg = <0x804000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + resets = <&syscon ASPEED_RESET_PCIE_RC_O>; + reset-names = "perst"; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcierc1_default>; + aspeed,pciephy = <&pcie_phy1>; + ranges; + }; + }; + gfx: display@1e6e6000 { compatible = "aspeed,ast2600-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; -- 2.43.0