From: Jacky Chou <jacky_chou@aspeedtech.com>
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <mani@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>,
<andrew@codeconstruct.com.au>, <linux-aspeed@lists.ozlabs.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <openbmc@lists.ozlabs.org>, <linux-gpio@vger.kernel.org>,
<linus.walleij@linaro.org>, <p.zabel@pengutronix.de>,
<BMC-SW@aspeedtech.com>
Subject: [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header
Date: Tue, 15 Jul 2025 11:43:18 +0800 [thread overview]
Message-ID: <20250715034320.2553837-9-jacky_chou@aspeedtech.com> (raw)
In-Reply-To: <20250715034320.2553837-1-jacky_chou@aspeedtech.com>
According to PCIe specification, add FMT and TYPE definition
for TLP header. And also add macro to combine FMT and TYPE to
1 byte.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
include/uapi/linux/pci_regs.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index a3a3e942dedf..700b915e00f5 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1230,4 +1230,36 @@
#define PCI_DVSEC_CXL_PORT_CTL 0x0c
#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
+/* Fmt[2:0] encoding for TLP Header */
+#define PCI_TLP_FMT_3DW_NO_DATA 0x0 // 3DW header, no data
+#define PCI_TLP_FMT_4DW_NO_DATA 0x1 // 4DW header, no data
+#define PCI_TLP_FMT_3DW_DATA 0x2 // 3DW header, with data
+#define PCI_TLP_FMT_4DW_DATA 0x3 // 4DW header, with data
+#define PCI_TLP_FMT_PREFIX 0x4 // Prefix header
+
+/* Type[4:0] encoding for TLP Header */
+#define PCI_TLP_TYPE_MEM_RD 0x00 // Memory Read Request
+#define PCI_TLP_TYPE_MEM_RDLK 0x01 // Memory Read Lock Request
+#define PCI_TLP_TYPE_MEM_WR 0x00 // Memory Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_IO_RD 0x02 // IO Read Request
+#define PCI_TLP_TYPE_IO_WR 0x02 // IO Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_CFG0_RD 0x04 // Config Type 0 Read Request
+#define PCI_TLP_TYPE_CFG0_WR 0x04 // Config Type 0 Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_CFG1_RD 0x05 // Config Type 1 Read Request
+#define PCI_TLP_TYPE_CFG1_WR 0x05 // Config Type 1 Write Request (Fmt must be with data)
+#define PCI_TLP_TYPE_MSG 0x10 // Message Request (see routing field)
+#define PCI_TLP_TYPE_MSGD 0x11 // Message Request with Data (see routing field)
+#define PCI_TLP_TYPE_CPL 0x0A // Completion without Data
+#define PCI_TLP_TYPE_CPLD 0x0A // Completion with Data (Fmt must be with data)
+#define PCI_TLP_TYPE_CPLLCK 0x0B // Completion Locked
+#define PCI_TLP_TYPE_CPLDLCK 0x0B // Completion with Data Locked (Fmt must be with data)
+#define PCI_TLP_TYPE_FETCH_ADD 0x0C // Fetch and Add AtomicOp Request
+#define PCI_TLP_TYPE_SWAP 0x0D // Unconditional Swap AtomicOp Request
+#define PCI_TLP_TYPE_CMP_SWAP 0x0E // Compare and Swap AtomicOp Request
+#define PCI_TLP_TYPE_LOCAL_PREFIX 0x00 // Local TLP Prefix (Fmt = 0x4)
+#define PCI_TLP_TYPE_E2E_PREFIX 0x10 // End-to-End TLP Prefix (Fmt = 0x4)
+
+/* Macro to combine Fmt and Type into the 8-bit field */
+#define PCIE_TLP_FMT_TYPE(fmt, type) (((fmt) << 5) | ((type) & 0x1F))
+
#endif /* LINUX_PCI_REGS_H */
--
2.43.0
next prev parent reply other threads:[~2025-07-15 3:43 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-15 3:43 [PATCH v2 00/10] Add ASPEED PCIe Root Complex support Jacky Chou
2025-07-15 3:43 ` [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support Jacky Chou
2025-07-16 8:24 ` Krzysztof Kozlowski
2025-07-21 3:47 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 02/10] dt-bindings: soc: aspeed: Add ASPEED PCIe PHY support Jacky Chou
2025-07-16 8:23 ` Krzysztof Kozlowski
2025-07-15 3:43 ` [PATCH v2 03/10] dt-bindings: PCI: Add ASPEED PCIe RC support Jacky Chou
2025-07-16 8:27 ` Krzysztof Kozlowski
2025-07-21 3:44 ` 回覆: " Jacky Chou
2025-07-21 7:00 ` Krzysztof Kozlowski
2025-07-22 5:29 ` Jacky Chou
2025-07-15 3:43 ` [PATCH v2 04/10] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Jacky Chou
2025-07-16 8:27 ` Krzysztof Kozlowski
2025-07-21 3:32 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Jacky Chou
2025-07-15 3:43 ` [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-07-15 15:25 ` Rob Herring
2025-07-16 3:51 ` Jacky Chou
2025-07-20 22:22 ` Rob Herring
2025-07-21 3:21 ` 回覆: " Jacky Chou
2025-07-15 3:43 ` [PATCH v2 07/10] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-07-23 11:23 ` Linus Walleij
2025-08-27 3:08 ` Jacky Chou
2025-08-28 20:46 ` Linus Walleij
2025-08-29 5:44 ` Jacky Chou
2025-07-15 3:43 ` Jacky Chou [this message]
2025-07-15 15:41 ` [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header Bjorn Helgaas
2025-08-27 1:22 ` Jacky Chou
2025-07-15 20:13 ` kernel test robot
2025-07-15 3:43 ` [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver Jacky Chou
2025-07-15 13:51 ` Philipp Zabel
2025-08-21 7:22 ` Jacky Chou
2025-07-15 16:22 ` Bjorn Helgaas
2025-08-22 7:00 ` 回覆: " Jacky Chou
2025-08-22 15:36 ` Bjorn Helgaas
2025-08-27 3:35 ` Jacky Chou
2025-07-15 17:00 ` Markus Elfring
2025-08-27 3:45 ` Jacky Chou
2025-07-15 22:28 ` kernel test robot
2025-07-15 3:43 ` [PATCH v2 10/10] MAINTAINERS: " Jacky Chou
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