From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-acpi@vger.kernel.org>
Cc: Ben Cheatham <Benjamin.Cheatham@amd.com>
Subject: [PATCH 08/16] cxl/core: Enable CXL isolation interrupts
Date: Wed, 30 Jul 2025 16:47:10 -0500 [thread overview]
Message-ID: <20250730214718.10679-9-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20250730214718.10679-1-Benjamin.Cheatham@amd.com>
Add functions to enable and disable CXL isolation interrupts. Use these
functions to enable interrupts as part of isolation set up.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/core/core.h | 2 ++
drivers/cxl/core/pci.c | 22 ++++++++++++++++++++++
drivers/cxl/core/port.c | 10 +++++++++-
drivers/cxl/cxl.h | 1 +
4 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index a84151238e17..4702a1f27318 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -146,4 +146,6 @@ int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
u16 *return_code);
#endif
+void cxl_enable_isolation_interrupts(struct cxl_dport *dport);
+void cxl_disable_isolation_interrupts(struct cxl_dport *dport);
#endif /* __CXL_CORE_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index c4d8d9690214..89fb6d3854e3 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -1172,6 +1172,28 @@ int cxl_port_update_total_dports(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(cxl_port_update_total_dports, "CXL");
+void cxl_enable_isolation_interrupts(struct cxl_dport *dport)
+{
+ u32 ctrl;
+
+ ctrl = readl(dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+ ctrl |= CXL_ISOLATION_CTRL_MEM_INTR_ENABLE;
+ writel(ctrl, dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+
+ dev_dbg(dport->dport_dev, "Enabled CXL isolation interrupts\n");
+}
+
+void cxl_disable_isolation_interrupts(struct cxl_dport *dport)
+{
+ u32 ctrl;
+
+ ctrl = readl(dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+ ctrl &= ~CXL_ISOLATION_CTRL_MEM_INTR_ENABLE;
+ writel(ctrl, dport->regs.isolation + CXL_ISOLATION_CTRL_OFFSET);
+
+ dev_dbg(dport->dport_dev, "Disabled CXL isolation interrupts\n");
+}
+
void cxl_enable_isolation(struct cxl_dport *dport)
{
u32 ctrl;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index a36440e85647..90588bf927e0 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1236,6 +1236,9 @@ static void cxl_dport_free_interrupts(void *data)
struct cxl_dport *dport = data;
struct pci_dev *pdev = to_pci_dev(dport->dport_dev);
+ if (dport->regs.isolation)
+ cxl_disable_isolation_interrupts(dport);
+
info = pcie_cxl_dport_get_isolation_info(pdev);
if (!info)
return;
@@ -1272,7 +1275,12 @@ static int cxl_dport_setup_interrupts(struct device *host,
if (rc)
return rc;
- return devm_add_action_or_reset(host, cxl_dport_free_interrupts, dport);
+ rc = devm_add_action_or_reset(host, cxl_dport_free_interrupts, dport);
+ if (rc)
+ return rc;
+
+ cxl_enable_isolation_interrupts(dport);
+ return 0;
}
/**
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 9e3ca754251d..62b3ed188949 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -141,6 +141,7 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
#define CXL_ISOLATION_CAP_INTR_MASK GENMASK(31, 27)
#define CXL_ISOLATION_CTRL_OFFSET 0x8
#define CXL_ISOLATION_CTRL_MEM_ISO_ENABLE BIT(16)
+#define CXL_ISOLATION_CTRL_MEM_INTR_ENABLE BIT(26)
#define CXL_ISOLATION_STATUS_OFFSET 0xC
#define CXL_ISOLATION_STAT_MEM_ISO BIT(8)
#define CXL_ISOLATION_STAT_LNK_DOWN BIT(9)
--
2.34.1
next prev parent reply other threads:[~2025-07-30 21:49 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 21:47 [PATCH 00/16] CXL.mem error isolation support Ben Cheatham
2025-07-30 21:47 ` [PATCH 01/16] cxl/regs: Add cxl_unmap_component_regs() Ben Cheatham
2025-07-30 21:47 ` [PATCH 02/16] cxl/regs: Add CXL Isolation capability mapping Ben Cheatham
2025-07-30 21:47 ` [PATCH 03/16] PCI: PCIe portdrv: Add CXL Isolation service driver Ben Cheatham
2025-07-30 21:47 ` [PATCH 04/16] PCI: PCIe portdrv: Allocate CXL isolation MSI/-X vector Ben Cheatham
2025-08-04 21:39 ` Bjorn Helgaas
2025-08-06 17:58 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 05/16] PCI: PCIe portdrv: Add interface for getting CXL isolation IRQ Ben Cheatham
2025-07-31 5:59 ` Lukas Wunner
2025-07-31 13:13 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 06/16] cxl/core: Enable CXL.mem isolation Ben Cheatham
2025-07-30 21:47 ` [PATCH 07/16] cxl/core: Set up isolation interrupts Ben Cheatham
2025-07-30 21:47 ` Ben Cheatham [this message]
2025-07-30 21:47 ` [PATCH 09/16] cxl/core: Prevent onlining CXL memory behind isolated ports Ben Cheatham
2025-07-30 21:47 ` [PATCH 10/16] cxl/core: Enable CXL.mem timeout Ben Cheatham
2025-07-30 21:47 ` [PATCH 11/16] cxl/pci: Add isolation handler Ben Cheatham
2025-07-30 21:47 ` [PATCH 12/16] PCI: PCIe portdrv: Add cxl_isolation sysfs attributes Ben Cheatham
2025-07-30 21:47 ` [PATCH 13/16] cxl/core, PCI: PCIe portdrv: Add CXL timeout range programming Ben Cheatham
2025-08-04 21:39 ` Bjorn Helgaas
2025-08-06 17:58 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 14/16] ACPI: Add CXL isolation _OSC fields Ben Cheatham
2025-08-22 19:19 ` Rafael J. Wysocki
2025-07-30 21:47 ` [PATCH 15/16] cxl/core, cxl/acpi: Enable CXL isolation based on _OSC handshake Ben Cheatham
2025-07-30 21:47 ` [PATCH 16/16] cxl/core, cxl/acpi: Add CXL isolation notify handler Ben Cheatham
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