Re: [PATCH RFC v2 0/4] Disable ATS via iommu during PCI resets

[Jason Gunthorpe <jgg@nvidia.com>]

On Thu, Jul 31, 2025 at 09:10:59AM +0800, Ethan Zhao wrote:
> > invalidations when the FLR is triggered.
> > 
> > We have been talking about DPC internally, and I think it will need a
> > related, but different flow since DPC can unavoidably trigger ATC
> > invalidation timeouts/failures and we must sensibly handle them in the
> There is race window for software to handle.
> And for DPC containing data corruption as priority, seems not rational to
> issue notification to software and then do resetting. alternative
> way might be async modal support in iommu ATC invalidation path ?

DPC would still act in HW to prevent corruption, SW would learn about
it either through a DPC async notify or through an ATC timeout, then
SW can reprogram the IOMMU to disable ATS.

We can't make the invalidation path async, the invalidation must
succeed or the iommu itself must fully fence future access to the
now-invalidate memory - most likely by disabling ATS, blocking
accepting translated TLPs and flushing out all previously accepted
translated TLPs.

Once invalidation finishes there must not be any IOMMU access to the
memory that was invalidation, and this cannot fail.

Jason