From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75219219300; Wed, 6 Aug 2025 21:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754515395; cv=none; b=tqcxK9HmJl1sye/CullEH6TlF1PYfSfAWVpdWom3HNsW2eBzd4zVaFnFSkgp4yoQypSnE1npllOYcfp7W7k5hlsuvsGHtnwJPdxNbMkT/fkffwIUgz5fyj5nb72ptX7fToHMqZaKVyhj/ripDT4iS/Ezc5lGrNzDCivLKy5NR3g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754515395; c=relaxed/simple; bh=WvNM36LLpqAXnbl/wdmEMZifs8nyq0/j+UYBi/yIlgs=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=rT7uL6iiXjVMqvQrd7irFuK8I8EHWtjagj4/vRP2k3VQhZ+8F772Gjggd7zTcIicsZ/MAzB5klXx3vF9jiPkRJw5udzE2caLdGWgH/py/fojg63VyA5yziQVQpkYSS0og5KoXWWViz4KzIktBHIbp9Ce/qYhGo/VTsLcULXYvoo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CDk+AGbK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CDk+AGbK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D71D8C4CEE7; Wed, 6 Aug 2025 21:23:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754515394; bh=WvNM36LLpqAXnbl/wdmEMZifs8nyq0/j+UYBi/yIlgs=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=CDk+AGbKnZ0zUSLo2BQ/QF7bkKyXufZl1i8fDdqO06ZkN4aLTfEgkx+8vbQyqxSl6 J1uSa7gmRTiuOAbqTVDtfWFzK7Re8M8bOmcBqr+WUohnf0FWM1sXsKfaAcaJykqj/v wHHkQr6lLxyIImcdgNSsQ6IAYVPJC6ja5xIOH2htdE6+b5Ca/aFmzuwW0ouOMtH6my 9sSZyyycrN7gRgF2X/Von4E6/z5K/+K9QBTisFzNhwPCXVwziU2sdw3rxS6fpXFXlq Ww438BAtKjWIUeYO8FbmkhxKFGccdhK6TGhzGOidLrixS3HSlPHAbI9mZ0jAEfblFj EeoI/2Mi9763g== Date: Wed, 6 Aug 2025 16:23:12 -0500 From: Bjorn Helgaas To: Marcos Del Sol Vives Cc: linux-kernel@vger.kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org Subject: Re: [PATCH] pci: disable MSI on RDC PCI to PCI-E bridges Message-ID: <20250806212312.GA18466@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250705233209.721507-1-marcos@orca.pet> On Sun, Jul 06, 2025 at 01:32:08AM +0200, Marcos Del Sol Vives wrote: > These bridges, present on Vortex86DX3 and Vortex86EX2 SoCs, do not > support MSIs. If enabled, interrupts generated by PCI-E devices never > reach the processor. > > I have contacted the manufacturer (DM&P) and they confirmed that PCI MSIs > need to be disabled for them. > > Signed-off-by: Marcos Del Sol Vives Applied to pci/msi for v6.18, thanks! > --- > drivers/pci/quirks.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index d7f4ee634263..f610ea45ca9e 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -2715,6 +2715,7 @@ static void quirk_disable_msi(struct pci_dev *dev) > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); > > /* > * The APC bridge device in AMD 780 family northbridges has some random > -- > 2.34.1 >