From: Bjorn Helgaas <helgaas@kernel.org>
To: Peter Chen <peter.chen@cixtech.com>
Cc: hans.zhang@cixtech.com, bhelgaas@google.com,
lpieralisi@kernel.org, kw@linux.com, mani@kernel.org,
robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, mpillai@cadence.com,
fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 09/13] PCI: Add Cix Technology Vendor and Device ID
Date: Fri, 15 Aug 2025 09:27:05 -0500 [thread overview]
Message-ID: <20250815142705.GA377241@bhelgaas> (raw)
In-Reply-To: <aJ6qTdA1f21SAr_l@nchen-desktop>
On Fri, Aug 15, 2025 at 11:32:29AM +0800, Peter Chen wrote:
> On 25-08-14 17:23:58, Bjorn Helgaas wrote:
> > On Wed, Aug 13, 2025 at 12:23:27PM +0800, hans.zhang@cixtech.com wrote:
> > > From: Hans Zhang <hans.zhang@cixtech.com>
> > >
> > > Add Cixtech P1 (internal name sky1) as a vendor and device ID for PCI
> > > devices. This ID will be used by the CIX Sky1 PCIe host controller driver.
> > >
> > > Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
> > > ---
> > > include/linux/pci_ids.h | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> > > index 92ffc4373f6d..24b04d085920 100644
> > > --- a/include/linux/pci_ids.h
> > > +++ b/include/linux/pci_ids.h
> > > @@ -2631,6 +2631,9 @@
> > >
> > > #define PCI_VENDOR_ID_CXL 0x1e98
> > >
> > > +#define PCI_VENDOR_ID_CIX 0x1f6c
> > > +#define PCI_DEVICE_ID_CIX_SKY1 0x0001
> >
> > I only see these used once in this series, so they probably should be
> > defined in the file that uses them, per the comment at the top of this
> > file.
> >
> > Also, https://pcisig.com/membership/member-companies?combine=0x1f6c
> > doesn't show 0x1f6c as assigned to CIX. That database often seems
> > incomplete, but please double check to make sure the ID is actually
> > reserved.
>
> Would you please check below:
> https://pcisig.com/membership/member-companies?combine=1f6c
Thanks, sorry if I've asked this before. Searching that pcisig
database always seems a little hit and miss.
Bjorn
next prev parent reply other threads:[~2025-08-15 14:27 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-13 4:23 [PATCH v7 00/13] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-08-13 4:23 ` [PATCH v7 01/13] PCI: cadence: Add support for modules for cadence controller builds hans.zhang
2025-08-14 21:25 ` Bjorn Helgaas
2025-08-13 4:23 ` [PATCH v7 02/13] PCI: cadence: Split PCIe controller header file hans.zhang
2025-08-14 21:16 ` Bjorn Helgaas
2025-08-18 2:01 ` Manikandan Karunakaran Pillai
2025-08-13 4:23 ` [PATCH v7 03/13] PCI: cadence: Add register definitions for HPA(High Perf Architecture) hans.zhang
2025-08-13 19:17 ` Krzysztof Kozlowski
2025-08-14 1:29 ` Manikandan Karunakaran Pillai
2025-08-14 21:35 ` Bjorn Helgaas
2025-08-13 4:23 ` [PATCH v7 04/13] PCI: cadence: Split PCIe EP support into common and specific functions hans.zhang
2025-08-14 21:41 ` Bjorn Helgaas
2025-08-13 4:23 ` [PATCH v7 05/13] PCI: cadence: Split PCIe RP " hans.zhang
2025-08-14 21:48 ` Bjorn Helgaas
2025-08-13 4:23 ` [PATCH v7 06/13] PCI: cadence: Split the common functions for PCIe controller support hans.zhang
2025-08-13 4:23 ` [PATCH v7 07/13] PCI: cadence: Add support for High Performance Arch(HPA) controller hans.zhang
2025-08-14 22:14 ` Bjorn Helgaas
2025-08-13 4:23 ` [PATCH v7 08/13] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-08-13 8:31 ` Rob Herring (Arm)
2025-08-13 9:12 ` Hans Zhang
2025-08-13 15:43 ` Rob Herring
2025-08-14 1:22 ` Hans Zhang
2025-08-13 19:08 ` Krzysztof Kozlowski
2025-08-14 1:26 ` Hans Zhang
2025-08-13 15:44 ` Rob Herring
2025-08-14 1:23 ` Hans Zhang
2025-08-13 4:23 ` [PATCH v7 09/13] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-08-14 22:23 ` Bjorn Helgaas
2025-08-15 3:32 ` Peter Chen
2025-08-15 14:27 ` Bjorn Helgaas [this message]
2025-08-13 4:23 ` [PATCH v7 10/13] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-08-13 19:16 ` Krzysztof Kozlowski
2025-08-14 1:29 ` Hans Zhang
2025-08-14 22:46 ` Bjorn Helgaas
2025-08-15 7:53 ` Hans Zhang
2025-08-13 4:23 ` [PATCH v7 11/13] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-08-13 4:23 ` [PATCH v7 12/13] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-08-13 4:23 ` [PATCH v7 13/13] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-08-13 19:14 ` [PATCH v7 00/13] Enhance the PCIe controller driver for next generation controllers Krzysztof Kozlowski
2025-08-14 1:37 ` Hans Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250815142705.GA377241@bhelgaas \
--to=helgaas@kernel.org \
--cc=bhelgaas@google.com \
--cc=cix-kernel-upstream@cixtech.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fugang.duan@cixtech.com \
--cc=guoyin.chen@cixtech.com \
--cc=hans.zhang@cixtech.com \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=kwilczynski@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=mpillai@cadence.com \
--cc=peter.chen@cixtech.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).