Linux PCI subsystem development
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From: Bjorn Helgaas <helgaas@kernel.org>
To: Randolph Lin <randolph@andestech.com>
Cc: linux-pci@vger.kernel.org, ben717@andestech.com, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, jingoohan1@gmail.com,
	mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org,
	bhelgaas@google.com, randolph.sklin@gmail.com,
	tim609@andestech.com
Subject: Re: [PATCH 2/6] PCI: dwc: Add outbound ATU range check callback
Date: Wed, 20 Aug 2025 10:52:36 -0500	[thread overview]
Message-ID: <20250820155236.GA626208@bhelgaas> (raw)
In-Reply-To: <20250820111843.811481-3-randolph@andestech.com>

On Wed, Aug 20, 2025 at 07:18:39PM +0800, Randolph Lin wrote:
> Introduce a callback for outbound ATU range checking to support
> range validations specific to cases that deviate from the generic
> check.
> 
> Signed-off-by: Randolph Lin <randolph@andestech.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 18 +++++++++++++-----
>  drivers/pci/controller/dwc/pcie-designware.h |  3 +++
>  2 files changed, 16 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 89aad5a08928..f410aefaeb5e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -535,12 +535,20 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
>  	u32 retries, val;
>  	u64 limit_addr;
>  
> -	limit_addr = parent_bus_addr + atu->size - 1;
> +	if (pci->ops && pci->ops->outbound_atu_check) {
> +		val = pci->ops->outbound_atu_check(pci, atu, &limit_addr);

The return is not a "val" and not a "u32".  It should be named "ret"
or similar.  Should be "int" since the callback and
dw_pcie_prog_outbound_atu() return "int".  But see below for possible
signature change.

Also not 100% convinced this is needed, see other patch where this is
implemented.

> +		if (val)
> +			return val;
> +	} else {
> +		limit_addr = parent_bus_addr + atu->size - 1;
>  
> -	if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
> -	    !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
> -	    !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> -		return -EINVAL;
> +		if ((limit_addr & ~pci->region_limit) !=
> +		    (parent_bus_addr & ~pci->region_limit) ||
> +		    !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
> +		    !IS_ALIGNED(atu->pci_addr, pci->region_align) ||
> +		    !atu->size) {
> +			return -EINVAL;
> +		}
>  	}
>  
>  	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 00f52d472dcd..40dd2c83b1c7 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -469,6 +469,9 @@ struct dw_pcie_ep {
>  
>  struct dw_pcie_ops {
>  	u64	(*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
> +	u32	(*outbound_atu_check)(struct dw_pcie *pcie,
> +				      const struct dw_pcie_ob_atu_cfg *atu,
> +				      u64 *limit_addr);

I have kind of an allergic reaction to things named "check" because
the name doesn't suggest anything about what the function does or what
it will return.  For bool functions, I prefer a name that's a
predicate that can be either true or false, e.g., "valid".

This isn't a bool, but possibly *could* be, e.g.,
"outbound_atu_addr_valid()".  Then the caller would be something like:

  if (!pci->ops->outbound_atu_addr_valid(...))
    return -EINVAL;

  reply	other threads:[~2025-08-20 15:52 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-20 11:18 [PATCH 0/6] Add support for Andes Qilai SoC PCIe controller Randolph Lin
2025-08-20 11:18 ` [PATCH 1/6] riscv: dts: andes: Define dma-ranges for coherent port Randolph Lin
2025-08-20 11:18 ` [PATCH 2/6] PCI: dwc: Add outbound ATU range check callback Randolph Lin
2025-08-20 15:52   ` Bjorn Helgaas [this message]
2025-08-20 11:18 ` [PATCH 3/6] dt-bindings: Add Andes QiLai PCIe support Randolph Lin
2025-08-21  6:11   ` Krzysztof Kozlowski
2025-08-20 11:18 ` [PATCH 4/6] riscv: dts: andes: Add PCIe node into the QiLai SoC Randolph Lin
2025-08-20 11:18 ` [PATCH 5/6] PCI: andes: Add Andes QiLai SoC PCIe host driver support Randolph Lin
2025-08-20 15:54   ` Bjorn Helgaas
2025-08-29  9:41     ` Randolph Lin
2025-09-08 22:07       ` Bjorn Helgaas
2025-09-09  8:14         ` Randolph Lin
2025-09-09 15:02           ` Frank Li
2025-09-08  7:02   ` Manivannan Sadhasivam
2025-09-09  6:59     ` Randolph Lin
2025-08-20 11:18 ` [PATCH 6/6] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Randolph Lin

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