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Tue, 26 Aug 2025 09:12:13 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 57Q9CBoU003404; Tue, 26 Aug 2025 09:12:11 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 48q6qksr62-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Aug 2025 09:12:11 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 57Q9CBbZ003391; Tue, 26 Aug 2025 09:12:11 GMT Received: from ziyuzhan-gv.ap.qualcomm.com (ziyuzhan-gv.qualcomm.com [10.64.66.102]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTPS id 57Q9CAhr003387 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Aug 2025 09:12:11 +0000 Received: by ziyuzhan-gv.ap.qualcomm.com (Postfix, from userid 4438065) id 7AB1951C; Tue, 26 Aug 2025 17:12:09 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang , Ziyue Zhang Subject: [PATCH v11 0/5] pci: qcom: Add QCS8300 PCIe support Date: Tue, 26 Aug 2025 17:12:00 +0800 Message-ID: <20250826091205.3625138-1-ziyue.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=Z/vsHGRA c=1 sm=1 tr=0 ts=68ad7a6e cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=QyXUC8HyAAAA:8 a=MByrn4WnkjAl5ObW7ywA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX9UbKYef1SGU5 rCkGvtkifKZ+tQq577Jz5yzxuiPQ4hBAJoGyTl0++Or/Qx0LT2ryQaP4GQwpQB0JZyzZXVN7Xx8 qkAU/x7Rg2J8iI9hmF6Bi8y3K3GTxl1Q0t4/6DxWAr/Oc3cs3jQIrzWxPiKU/eWn00Un5W6k4MY 80L9zUWdJbVdX1uAdsZHdmzU+pUvSWU34XRQvckpcBzqrzWxsRI1T0EDYaRNeHcIqtm0KA251Hw k+gzupbTmHLH/HbeqaD5CDla2Q5eJlgy1QhhiM7RaE8pLbcYO5RoaPocBBiA4JAV6oYMlYecbvd tFVHqfDmF9an0wFabbm7BLh7bXGiiFQEh1SXTGQiQYaHbIY2CkCqrEbD/dJOZEZZxfjyPHuldcL R3em9/M2 X-Proofpoint-GUID: bXOcsfKVh5Fx8uRiwKgNzulwDGHFNc8i X-Proofpoint-ORIG-GUID: bXOcsfKVh5Fx8uRiwKgNzulwDGHFNc8i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 suspectscore=0 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 This series depend on this patch https://lore.kernel.org/all/20250826-pakala-v2-3-74f1f60676c6@oss.qualcomm.com/ This series adds document, phy, configs support for PCIe in QCS8300. It also adds 'link_down' reset for sa8775p. Have follwing changes: - Add dedicated schema for the PCIe controllers found on QCS8300. - Add compatible for qcs8300 platform. - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- Changes in v11: - move phy/perst/wake to pcie bridge node (Mani) - Link to v10: https://lore.kernel.org/all/20250811071131.982983-1-ziyue.zhang@oss.qualcomm.com/ Changes in v10: - Update PHY max_items (Johan) - Link to v9: https://lore.kernel.org/all/20250725104037.4054070-1-ziyue.zhang@oss.qualcomm.com/ Changes in v9: - Fix DTB error (Vinod) - Link to v8: https://lore.kernel.org/all/20250714081529.3847385-1-ziyue.zhang@oss.qualcomm.com/ Changes in v8: - rebase sc8280xp-qmp-pcie-phy change to solve conflicts. - Add Fixes tag to phy change (Johan) - Link to v7: https://lore.kernel.org/all/20250625092539.762075-1-quic_ziyuzhan@quicinc.com/ Changes in v7: - rebase qcs8300-ride.dtsi change to solve conflicts. - Link to v6: https://lore.kernel.org/all/20250529035635.4162149-1-quic_ziyuzhan@quicinc.com/ Changes in v6: - move the qcs8300 and sa8775p phy compatibility entry into the list of PHYs that require six clocks - Update QCS8300 and sa8775p phy dt, remove aux clock. - Fixed compile error found by kernel test robot - Link to v5: https://lore.kernel.org/all/20250507031019.4080541-1-quic_ziyuzhan@quicinc.com/ Changes in v5: - Add QCOM PCIe controller version in commit msg (Mani) - Modify platform dts change subject (Dmitry) - Fixed compile error found by kernel test robot - Link to v4: https://lore.kernel.org/linux-phy/20241220055239.2744024-1-quic_ziyuzhan@quicinc.com/ Changes in v4: - Add received tag - Fixed compile error found by kernel test robot - Link to v3: https://lore.kernel.org/lkml/202412211301.bQO6vXpo-lkp@intel.com/T/#mdd63e5be39acbf879218aef91c87b12d4540e0f7 Changes in v3: - Add received tag(Rob & Dmitry) - Update pcie_phy in gcc node to soc dtsi(Dmitry & Konrad) - remove pcieprot0 node(Konrad & Mani) - Fix format comments(Konrad) - Update base-commit to tag: next-20241213(Bjorn) - Corrected of_device_id.data from 1.9.0 to 1.34.0. - Link to v2: https://lore.kernel.org/all/20241128081056.1361739-1-quic_ziyuzhan@quicinc.com/ Changes in v2: - Fix some format comments and match the style in x1e80100(Konrad) - Add global interrupt for PCIe0 and PCIe1(Konrad) - split the soc dtsi and the platform dts into two changes(Konrad) - Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@quicinc.com/ Ziyue Zhang (5): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for qcs8300 arm64: dts: qcom: qcs8300: enable pcie0 arm64: dts: qcom: qcs8300-ride: enable pcie0 interface arm64: dts: qcom: qcs8300: enable pcie1 arm64: dts: qcom: qcs8300-ride: enable pcie1 interface .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 17 +- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 84 +++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 310 +++++++++++++++++- 3 files changed, 394 insertions(+), 17 deletions(-) base-commit: 6c68f4c0a147c025ae0b25fab688c7c47964a02f -- 2.43.0