From: hans.zhang@cixtech.com
To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org
Cc: mpillai@cadence.com, fugang.duan@cixtech.com,
guoyin.chen@cixtech.com, peter.chen@cixtech.com,
cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Hans Zhang <hans.zhang@cixtech.com>
Subject: [PATCH v9 08/14] PCI: cadence: Update PCIe platform to use register offsets passed
Date: Mon, 1 Sep 2025 17:20:46 +0800 [thread overview]
Message-ID: <20250901092052.4051018-9-hans.zhang@cixtech.com> (raw)
In-Reply-To: <20250901092052.4051018-1-hans.zhang@cixtech.com>
From: Manikandan K Pillai <mpillai@cadence.com>
Update the PCIe Cadence platform to use register offsets that
are passed during probe of the platform.
Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
Co-developed-by: Hans Zhang <hans.zhang@cixtech.com>
Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
---
drivers/pci/controller/cadence/pcie-cadence-plat.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index b067a3296dd3..927ab5b8477c 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -31,6 +31,7 @@ static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
static const struct cdns_pcie_ops cdns_plat_ops = {
.cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
+ .link_up = cdns_pcie_linkup,
};
static int cdns_plat_pcie_probe(struct platform_device *pdev)
@@ -68,6 +69,11 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
rc = pci_host_bridge_priv(bridge);
rc->pcie.dev = dev;
rc->pcie.ops = &cdns_plat_ops;
+ rc->pcie.is_rc = data->is_rc;
+
+ /* Store the register bank offsets pointer */
+ rc->pcie.cdns_pcie_reg_offsets = data;
+
cdns_plat_pcie->pcie = &rc->pcie;
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
@@ -95,6 +101,11 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
ep->pcie.dev = dev;
ep->pcie.ops = &cdns_plat_ops;
+ ep->pcie.is_rc = data->is_rc;
+
+ /* Store the register bank offset pointer */
+ ep->pcie.cdns_pcie_reg_offsets = data;
+
cdns_plat_pcie->pcie = &ep->pcie;
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
--
2.49.0
next prev parent reply other threads:[~2025-09-01 9:21 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 9:20 [PATCH v9 00/14] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-09-01 9:20 ` [PATCH v9 01/14] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-09-01 9:20 ` [PATCH v9 02/14] PCI: cadence: Split PCIe controller header file hans.zhang
2025-09-01 9:20 ` [PATCH v9 03/14] PCI: cadence: Add register definitions for High Perf Architecture (HPA) hans.zhang
2025-09-01 9:20 ` [PATCH v9 04/14] PCI: cadence: Add helper functions for supporting " hans.zhang
2025-09-01 9:20 ` [PATCH v9 05/14] PCI: cadence: Move PCIe EP common functions to a separate file hans.zhang
2025-09-01 9:20 ` [PATCH v9 06/14] PCI: cadence: Move PCIe RP " hans.zhang
2025-09-01 9:20 ` [PATCH v9 07/14] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-09-01 9:20 ` hans.zhang [this message]
2025-09-01 9:20 ` [PATCH v9 09/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-09-01 9:20 ` [PATCH v9 10/14] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-09-01 9:20 ` [PATCH v9 11/14] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-09-01 9:20 ` [PATCH v9 12/14] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-09-01 9:20 ` [PATCH v9 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-09-01 9:20 ` [PATCH v9 14/14] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
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