From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18ABE2C08AC; Thu, 11 Sep 2025 07:56:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577382; cv=none; b=XwttPDhdQtf8ImqUeuFRprJobsi7qYjmb9PPDnlxj7ust1H7LoxWtRZjcq4oCPvqzSlqmO/nn+iJDO8AQz7nzHHhDRplNjYY+Mk666co0x9xfFSugu/UgfAOrtCG8jqc1swWfnRo7212jc0PHmFnR69jX/WErGH28Rc/dlXVsFE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577382; c=relaxed/simple; bh=NdLKAQlWUr0SnI1fWCp+SY3s4Yp8zDJc9KTErx0pre0=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Content-Type; b=J+PIdW+pWqEamePuK2udi79z2kH4TDfB7ufgmKiEZs7U5H/hO6TlaPulIEPnXgQn58oSAn21EpO9fKWk1uPD5N6xf6Gp+Ln5ZTrO+8teTIFq+smLY0APL3S/XWB6y/oHvodzInDtzo1QVkrWol2IBKzbdIDlh5tx7aIddUEzsZo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Pgc9bvnw; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Pgc9bvnw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757577381; x=1789113381; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=NdLKAQlWUr0SnI1fWCp+SY3s4Yp8zDJc9KTErx0pre0=; b=Pgc9bvnwgYzyS/oxiqWP3c9lw0aP9dn6rxdlL3PzA8mxIhVDLI7VWEIc PXuh849AQsKYhULkJnZnk7DSxbw9JozFxpOraUc/j7xLlm5D6kCDTjD7Y qz3Zh2FW3XvqrvYZ/V4Qcc2VyOW57vGxXyFD7tUNySMsZBPfRvBabDVW5 Edv4vebcGuwLbMEUn3zKVInFdT7tBMpXOkttM6wP6bImWYGr/7sZa0IJe WHFpyn+L6Qlwkc3v+P5xRvCIVIy3Y22KYq6QWDcZ3NF05oOk8KvXoYzyy OFLKYQtZLQWtlNrvxbZR1QUpDksD97mlyB6mXBb9oV/9ganG0ASleeG5L Q==; X-CSE-ConnectionGUID: S31QwmsYTrWq/jWcxfR/fg== X-CSE-MsgGUID: vFxmZBZaSb6V1uc1Zvmy7w== X-IronPort-AV: E=McAfee;i="6800,10657,11549"; a="58942205" X-IronPort-AV: E=Sophos;i="6.18,256,1751266800"; d="scan'208";a="58942205" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:56:20 -0700 X-CSE-ConnectionGUID: vPGNxPT3TFm13imjCknavQ== X-CSE-MsgGUID: PTSScRSiSEyaM2fCiqO+cQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,256,1751266800"; d="scan'208";a="210757574" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.187]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:56:13 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , ?UTF-8?q?Thomas=20Hellstr=C3=B6m?= Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 00/11] PCI: Resizable BAR improvements Date: Thu, 11 Sep 2025 10:55:54 +0300 Message-Id: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pci.c has been used as catch everything that doesn't fits elsewhere within PCI core and thus resizable BAR code has been placed there as well. Move Resizable BAR related code to a newly introduced rebar.c to reduce size of pci.c. After move, there are no pci_rebar_*() calls from pci.c indicating this is indeed well-defined subset of PCI core. Endpoint drivers perform Resizable BAR related operations which could well be performed by PCI core to simplify driver-side code. This series adds a few new API functions to that effect and converts the drivers to use the new APIs (in separate patches). While at it, also convert BAR sizes bitmask to u64 as PCIe spec already specifies more sizes than what will fit u32 to make the API typing more future-proof. The extra sizes beyond 128TB are not added at this point. These are based on pci/main, there are two minor conflicts with the work in pci/resource but I'm hesitant to base this on top of it as this is otherwise entirely independent. If we end up having to pull the bridge window select changes, there should be no reason why this does have to become collateral damage (so my suggestion, if this is good to go in this cycle, to take this into a separate branch than pci/resource and deal with those small conflicts while merging into pci/next). I've tested sysfs resize, i915, and xe BAR resizing functionality. In the case of xe, I did small hack patch as its resize is anyway broken as is because BAR0 pins the bridge window so resizing BAR2 fails. My hack caused other problems further down the road (likely because BAR0 is in use by the driver so releasing it messed assumptions xe driver has) but the BAR resize itself was working which was all I was interested to know. I'm not planning to pursue fixing the pinning problem within xe driver because the core changes to consider maximum size of the resizable BARs should take care of the main problem by different means. Some parts of this are to be used by the resizable BAR changes into the resource fitting/assingment logic but these seem to stand on their own so sending these out now to reduce the size of the other patch series. Ilpo Järvinen (11): PCI: Move Resizable BAR code into rebar.c PCI: Cleanup pci_rebar_bytes_to_size() and move into rebar.c PCI: Move pci_rebar_size_to_bytes() and export it PCI: Improve Resizable BAR functions kernel doc PCI: Add pci_rebar_size_supported() helper drm/i915/gt: Use pci_rebar_size_supported() drm/xe/vram: Use PCI rebar helpers in resize_vram_bar() PCI: Add pci_rebar_get_max_size() drm/xe/vram: Use pci_rebar_get_max_size() drm/amdgpu: Use pci_rebar_get_max_size() PCI: Convert BAR sizes bitmasks to u64 Documentation/driver-api/pci/pci.rst | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 +- drivers/gpu/drm/xe/xe_vram.c | 32 +- drivers/pci/Makefile | 2 +- drivers/pci/iov.c | 9 +- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/pci.c | 145 --------- drivers/pci/pci.h | 5 +- drivers/pci/rebar.c | 318 ++++++++++++++++++++ drivers/pci/setup-res.c | 78 ----- include/linux/pci.h | 15 +- 12 files changed, 354 insertions(+), 273 deletions(-) create mode 100644 drivers/pci/rebar.c base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 -- 2.39.5