Re: [PATCH] PCI: rcar-gen4: Add missing 1ms delay after PWR reset assertion

[Bjorn Helgaas <helgaas@kernel.org>]

On Thu, Sep 18, 2025 at 05:00:26AM +0200, Marek Vasut wrote:
> R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
> Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
> domain, after reset has been asserted by writing a matching reset bit into
> register SRCR, it is mandatory to wait 1ms.

> @@ -182,8 +182,10 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
>  		return ret;
>  	}
>  
> -	if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> +	if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
>  		reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> +		usleep_range(1000, 2000);

What would you think of "fsleep(1000)"?

I know there's controvery about fsleep(), but while the 1000 usec
lower bound is important, I think the selection of the 2000 usec upper
bound is pretty arbitrary and doesn't really justify spelling it out.

> +	}
>  
>  	val = readl(rcar->base + PCIEMSR0);
>  	if (rcar->drvdata->mode == DW_PCIE_RC_TYPE) {
> -- 
> 2.51.0
>