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Tue, 23 Sep 2025 09:21:40 -0700 (PDT) Received: from ziepe.ca ([130.41.10.202]) by smtp.gmail.com with ESMTPSA id af79cd13be357-84cb88e6969sm318223985a.2.2025.09.23.09.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 09:21:40 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1v15lr-0000000AxbL-2Bdg; Tue, 23 Sep 2025 13:21:39 -0300 Date: Tue, 23 Sep 2025 13:21:39 -0300 From: Jason Gunthorpe To: Manivannan Sadhasivam Cc: Bjorn Helgaas , Joerg Roedel , Will Deacon , Robin Murphy , Greg Kroah-Hartman , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Joerg Roedel , iommu@lists.linux.dev, Anders Roxell , Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , stable@vger.kernel.org Subject: Re: [PATCH 0/2] PCI: Fix ACS enablement for Root Ports in DT platforms Message-ID: <20250923162139.GC2547959@ziepe.ca> References: <20250910-pci-acs-v1-0-fe9adb65ad7d@oss.qualcomm.com> <20250918141102.GO1326709@ziepe.ca> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Sep 23, 2025 at 09:07:49PM +0530, Manivannan Sadhasivam wrote: > On Thu, Sep 18, 2025 at 11:11:02AM -0300, Jason Gunthorpe wrote: > > On Wed, Sep 10, 2025 at 11:09:19PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > > > This issue was already found and addressed with a quirk for a different device > > > from Microsemi with 'commit, aa667c6408d2 ("PCI: Workaround IDT switch ACS > > > Source Validation erratum")'. Apparently, this issue seems to be documented in > > > the erratum #36 of IDT 89H32H8G3-YC, which is not publicly available. > > > > This is a pretty broken device! I'm not sure this fix is good enough > > though. > > > > For instance if you reset a downstream device it should loose its RID > > and then the config cycles waiting for reset to complete will trigger SV > > and reset will fail? > > > > No. Resetting the Ethernet controller connected to the switch downstream port > doesn't fail and we could see that the reset succeeds. Reset it by up/down the PCI link? > Maybe the bus number was still captured by the device. Maybe, but I don't think that is spec conformat behavior. Jason