From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA69E27A47F; Tue, 23 Sep 2025 23:14:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758669282; cv=none; b=WGDmQ2hrBSyYWF2XSqjTdfVXd7G8+DLNOYmxvLPvcn6chxPA+LsivlIXYSU+Ha21ooKzjuoMcbOKgh1WUWjhvpe/6hUfgrq2e+3WSEginT6zZD3cFn5UzxgdHFQwMYBi3DrY5TF/C3yV0Ow8H+dgg0rYwiiJGcJUWYvT6Hiv3eQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758669282; c=relaxed/simple; bh=FIo/pZaUigBm9Ky7Kd/tXc9ekuQLyR4YIZcaFzQCtiQ=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=J30FNZNYpzbaO5Bys7KVu7Xdx7RyCmLJC+deNgYoATgTDdHnCsNPkXa+qoqGLUPm8aH+x91VoH4HYG7gHlDx5dztF/HoHAmi7BwggXUDoISgKJUHm9z8Bd7wCUndQSh9kS7VSjjZf+OEBq93ZKwRyoR7p4UWaLCHTIVvEgM/QJ0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i4h1dMVT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i4h1dMVT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0EF1BC4CEF5; Tue, 23 Sep 2025 23:14:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758669282; bh=FIo/pZaUigBm9Ky7Kd/tXc9ekuQLyR4YIZcaFzQCtiQ=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=i4h1dMVTNiSeEphauTed/sdFxAoQJwSsKrYvSrjvRA3dmEMTjfizecbRhCzSVHQbS eumTmaGee2OFoXPPcfJwKGIgYGuTXtGV1I0C5DbfjZ9a3HJOC7d6TwutwXwSvu/wpb PhVrkytG1zzKd7I0McAZQGrOSUjmde4TfevYlohf8zsOAc+XQ/4AVLXaJb+A/qrmcW ru/NfMUL+3MnX4x6rV9/FxqRYsxj/mEDS4XHxBGPs/RCojAuoAdhNMzn3c+OHoI1bS XF/ozk5qgvAZIiNFG+CmnxPQHqpVfTiSQMzrK5Kjt7VlCk92TAweuX/fd4YYffmSnh +n0Rh8Ln+RwXA== Date: Tue, 23 Sep 2025 18:14:40 -0500 From: Bjorn Helgaas To: manivannan.sadhasivam@oss.qualcomm.com Cc: Bjorn Helgaas , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, "David E. Box" , Kai-Heng Feng , "Rafael J. Wysocki" , Heiner Kallweit , Chia-Lin Kao Subject: Re: [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Message-ID: <20250923231440.GA2088746@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250922-pci-dt-aspm-v2-0-2a65cf84e326@oss.qualcomm.com> On Mon, Sep 22, 2025 at 09:46:43PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > Hi, > > This series is one of the 'let's bite the bullet' kind, where we have decided to > enable all ASPM and Clock PM states by default on devicetree platforms [1]. The > reason why devicetree platforms were chosen because, it will be of minimal > impact compared to the ACPI platforms. So seemed ideal to test the waters. > > Problem Statement > ================= > > Historically, PCI subsystem relied on the BIOS to enable ASPM and Clock PM > states for PCI devices before the kernel boot if the default states are > selected using: > > * Kconfig: CONFIG_PCIEASPM_DEFAULT=y, or > * cmdline: "pcie_aspm=off", or > * FADT: ACPI_FADT_NO_ASPM > > This was done to avoid enabling ASPM for the buggy devices that are known to > create issues with ASPM (even though they advertise the ASPM capability). But > BIOS is not at all a thing on most of the non-x86 platforms. For instance, the > majority of the Embedded and Compute ARM based platforms using devicetree have > something called bootloader, which is not anyway near the standard BIOS used in > x86 based platforms. And these bootloaders wouldn't touch PCIe at all, unless > they boot using PCIe storage, even then there would be no guarantee that the > ASPM states will get enabled. Another example is the Intel's VMD domain that is > not at all configured by the BIOS. But, this series is not enabling ASPM/Clock > PM for VMD domain. I hope it will be done similarly in the future patches. > > Solution > ======== > > So to avoid relying on BIOS, it was agreed [2] that the PCI subsystem has to > enable ASPM and Clock PM states based on the device capability. If any devices > misbehave, then they should be quirked accordingly. > > First patch of this series introduces two helper functions to enable all ASPM > and Clock PM states if of_have_populated_dt() is true. Second patch drops the > custom ASPM enablement code from the pcie-qcom driver as it is no longer needed. > > Testing > ======= > > This series is tested on Lenovo Thinkpad T14s based on Snapdragon X1 SoC. All > supported ASPM states are getting enabled for both the NVMe and WLAN devices by > default. > > [1] https://lore.kernel.org/linux-pci/a47sg5ahflhvzyzqnfxvpk3dw4clkhqlhznjxzwqpf4nyjx5dk@bcghz5o6zolk > [2] https://lore.kernel.org/linux-pci/20250828204345.GA958461@bhelgaas > > Changes in v2: > > - Used of_have_populated_dt() instead of CONFIG_OF to identify devicetree > platforms > - Renamed the override helpers and changed the override print > - Moved setting the default state back to the original place and only kept the > override in helpers > > Signed-off-by: Manivannan Sadhasivam > --- > Manivannan Sadhasivam (2): > PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for devicetree platforms > PCI: qcom: Remove the custom ASPM enablement code > > drivers/pci/controller/dwc/pcie-qcom.c | 32 -------------------------- > drivers/pci/pcie/aspm.c | 42 ++++++++++++++++++++++++++++++++-- > 2 files changed, 40 insertions(+), 34 deletions(-) I tentatively put this on pci/aspm and included it in pci/next. I think it's too late in the cycle to include this for v6.18, so I'll probably defer it until v6.19, but maybe we can start getting a little more testing.