From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B0AA18E3F; Wed, 24 Sep 2025 12:30:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758717011; cv=none; b=sm2PoLRfNdd7JyVJ+pOX3m6SqoCDqJfzGSY70/9QshNvAAzbP4g9Yb7SRqzwwLngQOMQyahtuvyHmjYCHYRpgXvIohMQez3e37IMgaplzi6ophJPuAXvV6HSGBHfSIWu17ZJCInZSokgAqvms3Gn6fb9MSyON5cD2GhETTPdqUc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758717011; c=relaxed/simple; bh=1/FUivANIkJMUDEE5QPqxlsnGmmnctoDup6MhovHyoQ=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=HinuTFFPRf1OSVGkMR9dtMxYfkFKmVZApLHVJTx7spQIkP/b8toR7Aaneo8R6MMCMnwt3tmmaMeriuL81BDp4UfjjHDIiZyG4V5ZAZ1zJKyYjBi2GCfh2z9E6DVzR3WxlHr8H563Eo5dm7jP8Dyl188I5jie9mgWRtx9UM1c4DI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 58OBST3P074422 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 24 Sep 2025 19:28:29 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Wed, 24 Sep 2025 19:28:29 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v4 0/5] Add support for Andes Qilai SoC PCIe controller Date: Wed, 24 Sep 2025 19:28:15 +0800 Message-ID: <20250924112820.2003675-1-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 58OBST3P074422 Add support for Andes Qilai SoC PCIe controller These patches introduce driver support for the PCIe controller on the Andes Qilai SoC. Signed-off-by: Randolph Lin --- Changes in v4: - Add .post_init callback for enabling IOCP cache. - Sort by vender name in Kconfig - Using PROBE_PREFER_ASYNCHRONOUS as default probe type. - Made minor adjustments based on the reviewer's suggestions. --- Changes in v3: - Remove outbound ATU address range validation callback and logic. - Add logic to skip failed outbound iATU configuration and continue. - Using PROBE_PREFER_ASYNCHRONOUS as default probe type. - Made minor adjustments based on the reviewer's suggestions. --- Changes in v2: - Remove the patch that adds the dma-ranges property to the SoC node. - Add dma-ranges to the PCIe parent node bus node. - Refactor and rename outbound ATU address range validation callback and logic. - Use parent_bus_offset instead of cpu_addr_fixup(). - Using PROBE_DEFAULT_STRATEGY as default probe type. - Made minor adjustments based on the reviewer's suggestions. Randolph Lin (5): PCI: dwc: Skip failed outbound iATU and continue dt-bindings: PCI: Add Andes QiLai PCIe support riscv: dts: andes: Add PCIe node into the QiLai SoC PCI: andes: Add Andes QiLai SoC PCIe host driver support MAINTAINERS: Add maintainers for Andes QiLai PCIe driver .../bindings/pci/andestech,qilai-pcie.yaml | 103 +++++++++ MAINTAINERS | 7 + arch/riscv/boot/dts/andes/qilai.dtsi | 112 ++++++++++ drivers/pci/controller/dwc/Kconfig | 13 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-andes-qilai.c | 198 ++++++++++++++++++ .../pci/controller/dwc/pcie-designware-host.c | 9 +- 7 files changed, 439 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c -- 2.34.1