From: Bjorn Helgaas <helgaas@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@oss.qualcomm.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
"Konrad Dybcio" <konrad.dybcio@oss.qualcomm.com>
Subject: Re: [PATCH] PCI: dwc: Support 16-lane operation
Date: Fri, 26 Sep 2025 16:03:45 -0500 [thread overview]
Message-ID: <20250926210345.GA2267761@bhelgaas> (raw)
In-Reply-To: <20250926-topic-pcie_16ln-v1-1-c249acc18790@oss.qualcomm.com>
On Fri, Sep 26, 2025 at 02:22:45PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Some hosts support 16 lanes of PCIe. Make num-lanes accept that number.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Applied to pci/controller/dwc, hoping for v6.18.
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 3 +++
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index fce15582c22a93167c6f03c0e3ae74f3d0e68b1a..1d7c2b27005f757d272fe78c4df48daa6628f0a3 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -774,6 +774,9 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> case 8:
> plc |= PORT_LINK_MODE_8_LANES;
> break;
> + case 16:
> + plc |= PORT_LINK_MODE_16_LANES;
> + break;
> default:
> dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
> return;
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index a333ab0b0bbd8c2fc0ee32a5619696178c6b7aa2..ae11a78cc5b9a4202794cfa515e1ee496a4f47c2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -90,6 +90,7 @@
> #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
> #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
> #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
> +#define PORT_LINK_MODE_16_LANES PORT_LINK_MODE(0x1f)
>
> #define PCIE_PORT_LANE_SKEW 0x714
> #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)
>
> ---
> base-commit: 8e2755d7779a95dd61d8997ebce33ff8b1efd3fb
> change-id: 20250926-topic-pcie_16ln-8b505b7909f4
>
> Best regards,
> --
> Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
prev parent reply other threads:[~2025-09-26 21:03 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-26 12:22 [PATCH] PCI: dwc: Support 16-lane operation Konrad Dybcio
2025-09-26 21:03 ` Bjorn Helgaas [this message]
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