From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68400311C2E; Tue, 14 Oct 2025 12:09:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760443769; cv=none; b=Qf0l9KuzngBw/GYr75L52hsbtSAOiLxpzDF5J73qJ5W5O2g++p5JZtREPE4UUm3CUSgGkl9y2Pe2ofACMr6UUZvRhc9DALUQSJaVXoN3r2O9t40dNY7iZNy/o+J2NFQu+tevDMhLdXGdwI5I3fWLQu5CdIleMQn9uJqa6vMzwTI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760443769; c=relaxed/simple; bh=LKggEBidnDaoYAZy2tX0K+iAOnLSLC3Hm2DoyOcDOqc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qz7H4MOf4UccgYu4mC1Nj9nTD5Mw3l/UR19s9Ev80WmVWDhFGjHSqucc2mZZ6DeNM2u4+oqZ6AFH4uww1aog6vt5HYGqZXjZPnFqf+OzhXvLLIvOp9v2jxJkc0jaAk87f77Jh9hn6+5Omd1rtMZd8o513Xj5N0vu85YYI8+TjrQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 59EC3wVo060867 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 14 Oct 2025 20:03:58 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 14 Oct 2025 20:03:58 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v8 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC Date: Tue, 14 Oct 2025 20:03:47 +0800 Message-ID: <20251014120349.656553-4-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251014120349.656553-1-randolph@andestech.com> References: <20251014120349.656553-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 59EC3wVo060867 Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Signed-off-by: Randolph Lin --- arch/riscv/boot/dts/andes/qilai.dtsi | 106 +++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi index de3de32f8c39..afa7b75a7e7a 100644 --- a/arch/riscv/boot/dts/andes/qilai.dtsi +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -182,5 +182,111 @@ uart0: serial@30300000 { reg-io-width = <4>; no-loopback-test; }; + + bus@80000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>, + <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>, + <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>; + + pcie@80000000 { + compatible = "andestech,qilai-pcie"; + device_type = "pci"; + reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04000000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names = "dbi", "apb", "config"; + + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>; + + #interrupt-cells = <1>; + interrupts = <0xf 0x4>; + interrupt-names = "msi"; + interrupt-parent = <&plic>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 1 &plic 0xf 0x4>, + <0 0 0 2 &plic 0xf 0x4>, + <0 0 0 3 &plic 0xf 0x4>, + <0 0 0 4 &plic 0xf 0x4>; + }; + }; + + bus@a0000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>, + <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>, + <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>; + + pcie@a0000000 { + compatible = "andestech,qilai-pcie"; + device_type = "pci"; + reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04001000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names = "dbi", "apb", "config"; + + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells = <1>; + interrupts = <0xe 0x4>; + interrupt-names = "msi"; + interrupt-parent = <&plic>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 1 &plic 0xe 0x4>, + <0 0 0 2 &plic 0xe 0x4>, + <0 0 0 3 &plic 0xe 0x4>, + <0 0 0 4 &plic 0xe 0x4>; + }; + }; + + bus@c0000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>, + <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>, + <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>; + + pcie@c0000000 { + compatible = "andestech,qilai-pcie"; + device_type = "pci"; + reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04002000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names = "dbi", "apb", "config"; + + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells = <1>; + interrupts = <0xd 0x4>; + interrupt-names = "msi"; + interrupt-parent = <&plic>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 1 &plic 0xd 0x4>, + <0 0 0 2 &plic 0xd 0x4>, + <0 0 0 3 &plic 0xd 0x4>, + <0 0 0 4 &plic 0xd 0x4>; + }; + }; + }; }; -- 2.34.1