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Tue, 14 Oct 2025 15:57:00 -0400 (EDT) Date: Tue, 14 Oct 2025 13:56:58 -0600 From: Alex Williamson To: ALOK TIWARI Cc: Bjorn Helgaas , donald.d.dugger@intel.com, linux-pci@vger.kernel.org Subject: Re: [QUERY] Is there a reason pci_quirk_enable_intel_rp_mpc_acs() uses pci_write_config_word() Message-ID: <20251014135658.1afeff57@shazbot.org> In-Reply-To: <67958fbe-fa61-4ea4-8040-c6b8d0313d57@oracle.com> References: <67958fbe-fa61-4ea4-8040-c6b8d0313d57@oracle.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 14 Oct 2025 10:57:39 +0530 ALOK TIWARI wrote: > Hi, > > function pci_quirk_enable_intel_rp_mpc_acs() in > drivers/pci/quirks.c, I noticed that the code reads a 32-bit value from > INTEL_MPC_REG using pci_read_config_dword(), but writes it back using > pci_write_config_word(). > > The relevant lines are: > > pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); > if (!(mpc & INTEL_MPC_REG_IRBNCE)) { > pci_info(dev, "Enabling MPC IRBNCE\n"); > mpc |= INTEL_MPC_REG_IRBNCE; > pci_write_config_word(dev, INTEL_MPC_REG, mpc); > } > > Given that: > /* Miscellaneous Port Configuration register */ > #define INTEL_MPC_REG 0xd8 > /* MPC: Invalid Receive Bus Number Check Enable */ > #define INTEL_MPC_REG_IRBNCE (1 << 26) > > the IRBNCE bit is in the upper 16 bits of this 32-bit register. > It seems that using pci_write_config_word() would not actually update > that bit. > > is there a specific hardware reason for using a 16-bit write? It looks like a typo to me. Please post a formal fix. Thanks, Alex > --- > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index 214ed060ca1b..1bd6e70058b5 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -5312,7 +5312,7 @@ static void > pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) > if (!(mpc & INTEL_MPC_REG_IRBNCE)) { > pci_info(dev, "Enabling MPC IRBNCE\n"); > mpc |= INTEL_MPC_REG_IRBNCE; > - pci_write_config_word(dev, INTEL_MPC_REG, mpc); > + pci_write_config_dword(dev, INTEL_MPC_REG, mpc); > } > } >