Linux PCI subsystem development
 help / color / mirror / Atom feed
From: kernel test robot <lkp@intel.com>
To: hans.zhang@cixtech.com, bhelgaas@google.com, helgaas@kernel.org,
	lpieralisi@kernel.org, kw@linux.com, mani@kernel.org,
	robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org
Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev,
	mpillai@cadence.com, fugang.duan@cixtech.com,
	guoyin.chen@cixtech.com, peter.chen@cixtech.com,
	cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Hans Zhang <hans.zhang@cixtech.com>
Subject: Re: [PATCH v10 04/10] PCI: cadence: Add support for High Perf Architecture (HPA) controller
Date: Mon, 20 Oct 2025 15:19:34 +0800	[thread overview]
Message-ID: <202510201553.x7S0SaZ1-lkp@intel.com> (raw)
In-Reply-To: <20251020042857.706786-5-hans.zhang@cixtech.com>

Hi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 211ddde0823f1442e4ad052a2f30f050145ccada]

url:    https://github.com/intel-lab-lkp/linux/commits/hans-zhang-cixtech-com/PCI-cadence-Add-module-support-for-platform-controller-driver/20251020-123246
base:   211ddde0823f1442e4ad052a2f30f050145ccada
patch link:    https://lore.kernel.org/r/20251020042857.706786-5-hans.zhang%40cixtech.com
patch subject: [PATCH v10 04/10] PCI: cadence: Add support for High Perf Architecture (HPA) controller
config: i386-buildonly-randconfig-002-20251020 (https://download.01.org/0day-ci/archive/20251020/202510201553.x7S0SaZ1-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251020/202510201553.x7S0SaZ1-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510201553.x7S0SaZ1-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/cadence/pcie-cadence-host-hpa.c:96:6: warning: variable 'ret' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
      96 |         if (rc->quirk_retrain_flag)
         |             ^~~~~~~~~~~~~~~~~~~~~~
   drivers/pci/controller/cadence/pcie-cadence-host-hpa.c:98:9: note: uninitialized use occurs here
      98 |         return ret;
         |                ^~~
   drivers/pci/controller/cadence/pcie-cadence-host-hpa.c:96:2: note: remove the 'if' if its condition is always true
      96 |         if (rc->quirk_retrain_flag)
         |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~
      97 |                 ret = cdns_pcie_retrain(pcie);
   drivers/pci/controller/cadence/pcie-cadence-host-hpa.c:84:18: note: initialize the variable 'ret' to silence this warning
      84 |         int retries, ret;
         |                         ^
         |                          = 0
   1 warning generated.


vim +96 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c

    79	
    80	static int cdns_pcie_hpa_host_wait_for_link(struct cdns_pcie *pcie)
    81	{
    82		struct device *dev = pcie->dev;
    83		struct cdns_pcie_rc *rc;
    84		int retries, ret;
    85	
    86		rc = container_of(pcie, struct cdns_pcie_rc, pcie);
    87	
    88		/* Check if the link is up or not */
    89		for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
    90			if (cdns_pcie_hpa_link_up(pcie)) {
    91				dev_info(dev, "Link up\n");
    92				return 0;
    93			}
    94			usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
    95		}
  > 96		if (rc->quirk_retrain_flag)
    97			ret = cdns_pcie_retrain(pcie);
    98		return ret;
    99	}
   100	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

  reply	other threads:[~2025-10-20  7:20 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-20  4:28 [PATCH v10 00/10] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-10-20  4:28 ` [PATCH v10 01/10] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-10-20  4:28 ` [PATCH v10 02/10] PCI: cadence: Split PCIe controller header file hans.zhang
2025-10-20  4:28 ` [PATCH v10 03/10] PCI: cadence: Move PCIe RP common functions to a separate file hans.zhang
2025-10-20  4:28 ` [PATCH v10 04/10] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-10-20  7:19   ` kernel test robot [this message]
2025-10-20  7:27     ` Hans Zhang
2025-10-31  9:11   ` Manivannan Sadhasivam
2025-10-31  9:20     ` Hans Zhang
2025-11-02  4:15     ` Manikandan Karunakaran Pillai
2025-11-02  5:40       ` Manivannan Sadhasivam
2025-11-02  5:51         ` Manikandan Karunakaran Pillai
2025-11-02 15:08           ` Manivannan Sadhasivam
2025-11-02 15:53             ` Manikandan Karunakaran Pillai
2025-11-02 16:39               ` Manivannan Sadhasivam
2025-10-20  4:28 ` [PATCH v10 05/10] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-10-20  4:28 ` [PATCH v10 06/10] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-10-20  4:28 ` [PATCH v10 07/10] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-10-31  9:15   ` Manivannan Sadhasivam
2025-10-31  9:22     ` Hans Zhang
2025-10-20  4:28 ` [PATCH v10 08/10] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-10-20  4:28 ` [PATCH v10 09/10] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-10-20  4:28 ` [PATCH v10 10/10] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-10-30  8:45 ` [PATCH v10 00/10] Enhance the PCIe controller driver for next generation controllers Hans Zhang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=202510201553.x7S0SaZ1-lkp@intel.com \
    --to=lkp@intel.com \
    --cc=bhelgaas@google.com \
    --cc=cix-kernel-upstream@cixtech.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=fugang.duan@cixtech.com \
    --cc=guoyin.chen@cixtech.com \
    --cc=hans.zhang@cixtech.com \
    --cc=helgaas@kernel.org \
    --cc=krzk+dt@kernel.org \
    --cc=kw@linux.com \
    --cc=kwilczynski@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=llvm@lists.linux.dev \
    --cc=lpieralisi@kernel.org \
    --cc=mani@kernel.org \
    --cc=mpillai@cadence.com \
    --cc=oe-kbuild-all@lists.linux.dev \
    --cc=peter.chen@cixtech.com \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox