From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75C0420766E; Fri, 24 Oct 2025 20:39:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761338366; cv=none; b=JVtsVboSAHblY/hbzBq4ZU1U2Zqfl4IQdEEvmmLg98xOwul/K+K2NPCpljMkUfEgsDJmXGh3mub3tukT1OANOQOk9BQ81+k1V0hcBksNItZ0sdKx5V68KIcZ2IYowNPTdiSvMo+FLn05cIJ3zciFtHI12sgXw7h5zCW9bFyIqg0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761338366; c=relaxed/simple; bh=nnTnBDGKXvWU3WYDEB3L7PEM0B9KPYgfbjggQZcxrE0=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; b=HGdUB48JAqU4vC+OSTxmy4VxXXpVVmx19xMlsuv17n5Eerg5MZF46B4zPIl7y5F/hCkov8hjFZv/JbuxufDY6sCpXDUFj+p5hAk3/JjR5DBH3s9P1Reb4yNhysKBvIDmhjlPTh0hCslc5idE0EqB8285T6+CJawH+1QzcCUHedc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z2zGaHcx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z2zGaHcx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CCEE4C4CEF1; Fri, 24 Oct 2025 20:39:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761338366; bh=nnTnBDGKXvWU3WYDEB3L7PEM0B9KPYgfbjggQZcxrE0=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=Z2zGaHcxF2LNrnLMJqLPWZhzVV1wDDWav76HGV8HAS8LukB473viCusYP/EP83vly 1DroxzbJfkKukObqkqh/VIchMmfMCsGcGOs8S0WFGZeWJquceY27S98gwfz3oLOz9q I/a9HhY4p6syTcqdnMUD6iLTTVC5nt3NBKm0GK06BpSIKBw7wy0lHl1agr5xY3V3fw vxmhhR93W0NkYvZx/YxK9CgB0CCV1eHmVA3MvQf3wpxtcAkzn0Km6HM4o8sNav8mL9 28wyXwQe7xUwFSpcvE8iU0PwPhdUZ7mY7IbUJgH0KEeawoOMtl/O/YorTMehiBheqt Z9DnFkl/JlhAA== Date: Fri, 24 Oct 2025 15:39:24 -0500 From: Bjorn Helgaas To: Johan Hovold Cc: linux-pci@vger.kernel.org, Manivannan Sadhasivam , Christian Zigotzky , FUKAUMI Naoki , Herve Codina , Diederik de Haas , Dragan Simic , linuxppc-dev@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Helgaas , Shawn Lin , Frank Li Subject: Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms Message-ID: <20251024203924.GA1361677@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: [+cc Shawn, Frank] On Fri, Oct 24, 2025 at 05:20:33PM +0200, Johan Hovold wrote: > On Fri, Oct 24, 2025 at 05:12:38PM +0200, Johan Hovold wrote: > > On Thu, Oct 23, 2025 at 01:06:26PM -0500, Bjorn Helgaas wrote: > > > From: Bjorn Helgaas > > > > > > f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for > > > devicetree platforms") enabled Clock Power Management and L1 PM > > > Substates, but those features depend on CLKREQ# and possibly > > > other device-specific configuration. We don't know whether > > > CLKREQ# is supported, so we shouldn't blindly enable Clock PM > > > and L1 PM Substates. > > > > > > Enable only ASPM L0s and L1, and only when both ends of the link > > > advertise support for them. > > > > > > Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") > ... > > > --- > > > I intend this for v6.18-rc3. > > > > Note that this will regress ASPM on Qualcomm platforms further by > > disabling L1SS for devices that do not use pwrctrl (e.g. NVMe). ASPM > > with pwrctrl is already broken since 6.15. [1] > > Actually, the 6.15 regression was fixed in 6.18-rc1 by the offending > commit, but pwrctrl devices will now also regress again. > > > Reverting also a729c1664619 ("PCI: qcom: Remove custom ASPM enablement > > code") should avoid the new regression until a proper fix for the 6.15 > > regression is in place. Help me think through this. I just sent a pull request [2] that includes df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms"). If all goes well, v6.18-rc3 will enable L0s and L1 (but not L1SS) on Qualcomm platforms. IIUC, if we then revert a729c1664619 ("PCI: qcom: Remove custom ASPM enablement code"), it will enable L1SS again, but since this is done in a dw_pcie_host_ops .post_init() hook, L1SS will only be enabled for devices powered on at qcom-pcie probe time. It will *not* be enabled for pwrctrl devices because .post_init() was run when those devices were powered off. I think this is the same as in v6.17. v6.18-rc1 enabled L1SS for everything, including pwrctrl devices, because it was done in the PCI enumeration path, not the host controller probe path. I think that enumeration is the right place to do this, but we need to figure out how to do it in a generic way. At a minimum, we need to know that CLKREQ# is supported, and some platforms like dw-rockchip also need device-specific configuration [3]. Bottom line, I think we need to revert a729c1664619 for v6.18 to get all ASPM states including L1SS enabled on Qualcomm platforms for non-pwrctrl devices. I'll post a patch for this. Then try to figure out how to make this work for pwrctrl devices for v6.19. Does this sound right? Bjorn > > [1] https://lore.kernel.org/lkml/aH4JPBIk_GEoAezy@hovoldconsulting.com/ [2] https://lore.kernel.org/r/20251024192903.GA1360890@bhelgaas [3] https://lore.kernel.org/r/1761187883-150120-1-git-send-email-shawn.lin@rock-chips.com