linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Anand Moon <linux.amoon@gmail.com>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Niklas Cassel" <cassel@kernel.org>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Hans Zhang" <18255117159@163.com>,
	"Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>,
	linux-pci@vger.kernel.org (open list:PCI NATIVE HOST BRIDGE AND
	ENDPOINT DRIVERS),
	linux-arm-kernel@lists.infradead.org (moderated
	list:ARM/Rockchip SoC support),
	linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC
	support), linux-kernel@vger.kernel.org (open list)
Cc: Anand Moon <linux.amoon@gmail.com>
Subject: [PATCH v1 2/2] PCI: dw-rockchip: Add runtime PM support to Rockchip PCIe driver
Date: Mon, 27 Oct 2025 20:25:30 +0530	[thread overview]
Message-ID: <20251027145602.199154-3-linux.amoon@gmail.com> (raw)
In-Reply-To: <20251027145602.199154-1-linux.amoon@gmail.com>

Add runtime power management support to the Rockchip DesignWare PCIe
controller driver by enabling devm_pm_runtime() in the probe function.
These changes allow the PCIe controller to suspend and resume dynamically,
improving power efficiency on supported platforms.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index b878ae8e2b3e..5026598d09f8 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -20,6 +20,7 @@
 #include <linux/of_irq.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/reset.h>
 
@@ -690,6 +691,20 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		goto deinit_phy;
 
+	ret = pm_runtime_set_suspended(dev);
+	if (ret)
+		goto disable_pm_runtime;
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret) {
+		ret = dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
+		goto deinit_clk;
+	}
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret)
+		goto disable_pm_runtime;
+
 	switch (data->mode) {
 	case DW_PCIE_RC_TYPE:
 		ret = rockchip_pcie_configure_rc(pdev, rockchip);
@@ -709,7 +724,10 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 
 	return 0;
 
+disable_pm_runtime:
+	pm_runtime_disable(dev);
 deinit_clk:
+	pm_runtime_no_callbacks(dev);
 	clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
 deinit_phy:
 	rockchip_pcie_phy_deinit(rockchip);
@@ -725,6 +743,9 @@ static void rockchip_pcie_remove(struct platform_device *pdev)
 	/* Perform other cleanups as necessary */
 	clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
 	rockchip_pcie_phy_deinit(rockchip);
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+	pm_runtime_no_callbacks(dev);
 }
 
 static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
-- 
2.50.1


  parent reply	other threads:[~2025-10-27 14:56 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27 14:55 [PATCH v1 0/2] Add runtime PM support to Rockchip DW PCIe driver Anand Moon
2025-10-27 14:55 ` [PATCH v1 1/2] PCI: dw-rockchip: Add remove callback for resource cleanup Anand Moon
2025-10-27 15:12   ` Nicolas Frattaroli
2025-10-27 16:31     ` Anand Moon
2025-10-27 17:17       ` Nicolas Frattaroli
2025-10-28  0:26   ` Shawn Lin
2025-10-28  9:34     ` Anand Moon
2025-10-29  0:28       ` Shawn Lin
2025-10-29  6:24         ` Anand Moon
2025-10-31  8:36   ` Manivannan Sadhasivam
2025-10-31 12:29     ` Nicolas Frattaroli
2025-10-31 15:08       ` Manivannan Sadhasivam
2025-10-27 14:55 ` Anand Moon [this message]
2025-10-28  0:44   ` [PATCH v1 2/2] PCI: dw-rockchip: Add runtime PM support to Rockchip PCIe driver Shawn Lin
2025-10-28  9:34     ` Anand Moon
2025-10-31  8:39   ` Manivannan Sadhasivam
2025-10-31 14:03     ` Anand Moon
2025-10-31 14:53       ` Manivannan Sadhasivam
2025-11-01  8:09         ` Anand Moon
2025-10-27 15:06 ` [PATCH v1 0/2] Add runtime PM support to Rockchip DW " Nicolas Frattaroli
2025-10-29  6:29   ` Anand Moon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251027145602.199154-3-linux.amoon@gmail.com \
    --to=linux.amoon@gmail.com \
    --cc=18255117159@163.com \
    --cc=bhelgaas@google.com \
    --cc=cassel@kernel.org \
    --cc=heiko@sntech.de \
    --cc=kwilczynski@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-rockchip@lists.infradead.org \
    --cc=lpieralisi@kernel.org \
    --cc=mani@kernel.org \
    --cc=nicolas.frattaroli@collabora.com \
    --cc=robh@kernel.org \
    --cc=shawn.lin@rock-chips.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).