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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2025 15:49:00.4076 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d12df7bc-958e-4ffa-4c95-08de17cbd822 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7107 In the NVIDIA vGPU RFC [1], the PCI configuration space access is required in nova-core for preparing gspVFInfo when vGPU support is enabled. This series is the following up of the discussion with Danilo for how to introduce support of PCI configuration space access in Rust PCI abstrations. v3: - Turn offset_valid() into a private function of kernel::io:Io. (Alex) - Separate try and non-try variants. (Danilo) - Move all the {try_}{read,write}{8,16,32,64} accessors to the I/O trait. (Danilo) - Replace the hardcoded MMIO type constraint with a generic trait bound so that register! macro can be used in other places. (Danilo) - Fix doctest. (John) - Add an enum for PCI configuration space size. (Danilo) - Refine the patch comments. (Bjorn) This ideas of this series are: - Factor out a common trait IoRegion for other accessors to share the same compiling/runtime check like before. - Factor the MMIO read/write macros from the define_read! and define_write! macros. Thus, define_{read, write}! can be used in other backend. In detail: * Introduce `call_mmio_read!` and `call_mmio_write!` helper macros to encapsulate the unsafe FFI calls. * Update `define_read!` and `define_write!` macros to delegate to the call macros. * Export `define_read` and `define_write` so they can be reused for other I/O backends (e.g. PCI config space). - Add a helper to query configuration space size. This is mostly for runtime check. - Implement the PCI configuration space access backend in PCI Abstractions. - Add tests for config space routines in rust PCI sample driver. Zhi Wang (5): rust: io: factor common I/O helpers into Io trait and specialize Mmio rust: io: factor out MMIO read/write macros rust: pci: add a helper to query configuration space size rust: pci: add config space read/write support sample: rust: pci: add tests for config space routines drivers/gpu/nova-core/regs/macros.rs | 90 +++++--- drivers/gpu/nova-core/vbios.rs | 1 + rust/kernel/devres.rs | 12 +- rust/kernel/io.rs | 333 +++++++++++++++++++++------ rust/kernel/io/mem.rs | 16 +- rust/kernel/io/poll.rs | 4 +- rust/kernel/pci.rs | 94 +++++++- samples/rust/rust_driver_pci.rs | 28 ++- 8 files changed, 444 insertions(+), 134 deletions(-) -- 2.47.3