From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45EF82FAC16; Sat, 1 Nov 2025 13:33:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762003988; cv=none; b=QOVYFzWGT1fAcXHSZanoIaIBUAUCTwBeE0n2pFwKAgjn+kJxNnxk4QqnQx5lt9q7eicQmq9qUHjU6igOYFLXO8R7b+xWicoULXeG8AnK12/Qwj6vJ6DV+UYTU08Pk5pQ/dRsnZf45lEdmmpV8fnN1qd4mCHqWNNJkQDxTw+8PFg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762003988; c=relaxed/simple; bh=Khddq10rDTNCJC+WhHqWSm+UChMJ0XNPjzUvEysQkxg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DnqEKBegxPN6jKbrPuDfKoNR9IKCZnw9ljbfHOGkSV31zVO3WD8cW3znKI7klWfHEWzBEqXAvWwb+93CHB7fbIt/SlZHVSx0zkDfPLNIyPTu/H2D2zQB8mq3eufiq/6a0b/Cxwy4UEDNNnVzFC50Cp4WrIX7sBiTmIEEGiYrZrw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=U1A0ycTn; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="U1A0ycTn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1762003979; bh=Khddq10rDTNCJC+WhHqWSm+UChMJ0XNPjzUvEysQkxg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=U1A0ycTnOTMFInmhlHARM/cxFDiIstBqvq2sakPc///cWFfjXxPA1tikJgWkiOhlB RNVX6BK5PfhpqFPpqz8lmtyT3gv8vtCBjJmyTKajba1RWMjL6p/bZ3Mt//xYnHh7aY T3PK7r0RcPkQUSS1pBZQXBMubn3iEKD9KNxBb5v4bn2vdtmK0gtTxMEPbCLkUl9JZw r5CQbItPouyXCXhwXPJjKf+aIM7tfr33SupCpWxJI7nMs02Bn5t6Lk75Ka+OUMmUqd 2wuCZWNWYGToSFhrIq9EfIUgnKQzXxm5hwrIqzWloCysutJvyse1RrIVV/3m4qRA6X 1gwrNXKrLYoGA== Received: from beast.luon.net (unknown [IPv6:2a10:3781:2531::8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sjoerd) by bali.collaboradmins.com (Postfix) with ESMTPSA id 566AA17E1414; Sat, 1 Nov 2025 14:32:59 +0100 (CET) Received: by beast.luon.net (Postfix, from userid 1000) id AAB2010E9D036; Sat, 01 Nov 2025 14:32:58 +0100 (CET) From: Sjoerd Simons Date: Sat, 01 Nov 2025 14:32:52 +0100 Subject: [PATCH v2 07/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable PCIe and USB Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251101-openwrt-one-network-v2-7-2a162b9eea91@collabora.com> References: <20251101-openwrt-one-network-v2-0-2a162b9eea91@collabora.com> In-Reply-To: <20251101-openwrt-one-network-v2-0-2a162b9eea91@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Lee Jones , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lorenzo Bianconi , Felix Fietkau Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, netdev@vger.kernel.org, Daniel Golle , Bryan Hinton , Sjoerd Simons X-Mailer: b4 0.14.3 Enable the PCIe controller and USB3 XHCI host on the OpenWrt One board. The USB controller is configured for USB 2.0 only mode, as the shared USB3/PCIe PHY is dedicated to PCIe functionality on this board. Signed-off-by: Sjoerd Simons --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 968b91f55bb27..5834273839c17 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -20,8 +20,53 @@ memory@40000000 { reg = <0 0x40000000 0 0x40000000>; device_type = "memory"; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pio { + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; }; &uart0 { status = "okay"; }; + +&usb_phy { + status = "okay"; +}; + +&xhci { + phys = <&u2port0 PHY_TYPE_USB2>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; -- 2.51.0