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Mon, 03 Nov 2025 07:15:03 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 03 Nov 2025 16:14:44 +0100 Subject: [PATCH 04/12] dt-bindings: PCI: qcom,pcie-qcs404: Move QCS404 to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251103-dt-bindings-pci-qcom-v1-4-c0f6041abf9b@linaro.org> References: <20251103-dt-bindings-pci-qcom-v1-0-c0f6041abf9b@linaro.org> In-Reply-To: <20251103-dt-bindings-pci-qcom-v1-0-c0f6041abf9b@linaro.org> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6892; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=fRCCTTQtkmskj6hjCG7g0ZK8BRFz/06lAV1QM0WwAQE=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBpCMbnZeQOrrJg5KNngoIPwnZo26ZOFZVh1gJSv TkQROidDveJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaQjG5wAKCRDBN2bmhouD 1waqD/sGI+q6pJqbi7PSXchPg9OI9ea+TiFFoPvPOyPpH1UsAyVSlpz9BtGnr8vyp7CV/mJ+2ej s48NLEVogMV5nJcI2XW6gwp5lIcB3LJv70Ejt5gCsWsi7TDTyPVtF/w5yUuX43TNb+TW6ZZEOzf p6f2HcxbefOGrLtY5SoDa6Ehv1CrRohKDPgXOElrZEEtLoLkQUGscdVJ+Y1MuSeTZHhVqK4rNO3 vspflW59xQdv7nvOMCtu+SJwycZI0G9SJ5CjlPKLgqkVS+Z2l7nlOB1LVaA42VtI54XPC2eF23i kM1280oCWqP2+uP5x0gasybk8S0xJ1VVP34i02AEvGs0iLm8xCWwwB2owFDzezCcNGGu85cR9ee FtD0aXBcokAEDlFYTXmCo208XC3c3cdAhnKO9Z3bghkmIs3MZZ3HmNT/u/p62geKiHhT5Sszv6Q YsQ/wnmTFubn0yjNgfJwnakNye7xhLfWOjxP5aZCz/jOIYe3yp5o3cdofho2Tx7C85NXgAP6Eol VIq+lunmlSpIOdC3i5cX2eWWTHmi+ILf4xwfL7NnPkqhREHLi9H3SzVq8oAK16bz3dw1vIV2EO9 JY4RlYo0a4hKZJe3QCfgnQgi5hhQsMjrN9lxW4klJW6F9AIdRBOef+3QW9oEAOJxvplezWgVorK clYoRi/8q9jE2Vw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move QCS404 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-qcs404.yaml | 131 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 33 ------ 2 files changed, 131 insertions(+), 33 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml new file mode 100644 index 000000000000..99b3ed43b87c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs404.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS404 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +properties: + compatible: + enum: + - qcom,pcie-qcs404 + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: elbi + - const: parf + - const: config + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iface # AHB clock + - const: aux + - const: master_bus # AXI Master clock + - const: slave_bus # AXI Slave clock + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + resets: + maxItems: 6 + + reset-names: + items: + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: pipe_sticky + - const: pwr + - const: ahb + +required: + - resets + - reset-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie@10000000 { + compatible = "qcom,pcie-qcs404"; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x07780000 0x2000>, + <0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ + <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ + + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 68cae47c2ef6..df58e52cc0b9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -29,7 +29,6 @@ properties: - qcom,pcie-ipq8074-gen3 - qcom,pcie-ipq9574 - qcom,pcie-msm8996 - - qcom,pcie-qcs404 - items: - enum: - qcom,pcie-ipq5332 @@ -149,7 +148,6 @@ allOf: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 - - qcom,pcie-qcs404 then: properties: reg: @@ -483,35 +481,6 @@ allOf: - const: msi7 - const: global - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-qcs404 - then: - properties: - clocks: - minItems: 4 - maxItems: 4 - clock-names: - items: - - const: iface # AHB clock - - const: aux # Auxiliary clock - - const: master_bus # AXI Master clock - - const: slave_bus # AXI Slave clock - resets: - minItems: 6 - maxItems: 6 - reset-names: - items: - - const: axi_m # AXI Master reset - - const: axi_s # AXI Slave reset - - const: axi_m_sticky # AXI Master Sticky reset - - const: pipe_sticky # PIPE sticky reset - - const: pwr # PWR reset - - const: ahb # AHB reset - - if: not: properties: @@ -526,7 +495,6 @@ allOf: - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 - qcom,pcie-ipq9574 - - qcom,pcie-qcs404 then: required: - power-domains @@ -588,7 +556,6 @@ allOf: - qcom,pcie-ipq4019 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - - qcom,pcie-qcs404 then: properties: interrupts: -- 2.48.1