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Mon, 03 Nov 2025 07:15:11 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 03 Nov 2025 16:14:48 +0100 Subject: [PATCH 08/12] dt-bindings: PCI: qcom,pcie-ipq4019: Move IPQ4019 to dedicated schema Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251103-dt-bindings-pci-qcom-v1-8-c0f6041abf9b@linaro.org> References: <20251103-dt-bindings-pci-qcom-v1-0-c0f6041abf9b@linaro.org> In-Reply-To: <20251103-dt-bindings-pci-qcom-v1-0-c0f6041abf9b@linaro.org> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7615; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=EdqAb+QTLdzor0jomhHKcam0nKS8WZX2EFMgXyS87bo=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBpCMbqqaZ9LTptcbEg4uhSefLjp+85I/Ut/mMVu H9nfwbNr06JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaQjG6gAKCRDBN2bmhouD 1/7JD/sFEdKV1keZziofkPvYVBb8IX16CWFlZfjn8Ro/QQ2o80DxPldefYyUijIseFZr+KyWyYv URU14WcfYGjNStpjW5YE4dhkJwET1yvPMLMEnneOkkuVsHE+hzBvQwGA2mm/SYSI3EewvR+/ckH s1LIW6jQ8QR9D9pXXgpPTmE6qCpH/tjZ+wjuKy1/V1SMN8s4s02RJlWr9/K5RvpCKRGsl9xNmuz dAyFyjB3enxj9nSPy4K4kNy1Ct5dV+gN9FGcoUECxQUJ+v0yNLUkKT6CY8Zf4vD2xmvfoI/9iJs ATMFLPc+ate6t8OCqPxyFg2IoTlm/XCA7WnpdYdNf7EjFLSKFklMpGh2oBX6LjSvndDvzKn5lBr YhANiNu2uzvgL7ki9D29dy9HeYRrCuUia+P1RBEbOvnFxVuRzxNOsmBmKSqCI+hwReAUgZWHYbo hvWRs7NZNdTOhymuhJUE6qjml0pYBABzFiZmhNP8ctpFON/apYYEs+bVcRQrx57yGe3ZMs41bUA Jioq5QKu67A8xLt8FjBJk0IUV2aV4fjmWQVITvfxkbIJG96gKO7G3OuujDezw1AnMHfw+HpKKAL Kf/9jeIRB5sYsTmLOj5+EUcBbMarrIpG6u03IHGC8CsTaBkocCFj0z55aMwhZNBNnZFwrLAJJUP RrNXPot3NCn4QeA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move IPQ4019 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-ipq4019.yaml | 146 +++++++++++++++++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 38 ------ 2 files changed, 146 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml new file mode 100644 index 000000000000..fd6ecd1c43a1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq4019.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ4019 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +properties: + compatible: + enum: + - qcom,pcie-ipq4019 + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: elbi + - const: parf + - const: config + + clocks: + maxItems: 3 + + clock-names: + items: + - const: aux + - const: master_bus # Master AXI clock + - const: slave_bus # Slave AXI clock + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + resets: + maxItems: 12 + + reset-names: + items: + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: pipe + - const: axi_m_vmid + - const: axi_s_xpu + - const: parf + - const: phy + - const: axi_m_sticky # AXI master sticky reset + - const: pipe_sticky + - const: pwr + - const: ahb + - const: phy_ahb + +required: + - resets + - reset-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie@40000000 { + compatible = "qcom,pcie-ipq4019"; + reg = <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x80000 0x2000>, + <0x40100000 0x1000>; + reg-names = "dbi", "elbi", "parf", "config"; + ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, + <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; + + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_AHB_CLK>, + <&gcc GCC_PCIE_AXI_M_CLK>, + <&gcc GCC_PCIE_AXI_S_CLK>; + clock-names = "aux", + "master_bus", + "slave_bus"; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + resets = <&gcc PCIE_AXI_M_ARES>, + <&gcc PCIE_AXI_S_ARES>, + <&gcc PCIE_PIPE_ARES>, + <&gcc PCIE_AXI_M_VMIDMT_ARES>, + <&gcc PCIE_AXI_S_XPU_ARES>, + <&gcc PCIE_PARF_XPU_ARES>, + <&gcc PCIE_PHY_ARES>, + <&gcc PCIE_AXI_M_STICKY_ARES>, + <&gcc PCIE_PIPE_STICKY_ARES>, + <&gcc PCIE_PWR_ARES>, + <&gcc PCIE_AHB_ARES>, + <&gcc PCIE_PHY_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "pipe", + "axi_m_vmid", + "axi_s_xpu", + "parf", + "phy", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb", + "phy_ahb"; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 992a7654626c..65caf5b5623d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -20,7 +20,6 @@ properties: - enum: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - - qcom,pcie-ipq4019 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq9574 @@ -140,7 +139,6 @@ allOf: contains: enum: - qcom,pcie-apq8064 - - qcom,pcie-ipq4019 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 then: @@ -258,40 +256,6 @@ allOf: items: - const: core # Core reset - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-ipq4019 - then: - properties: - clocks: - minItems: 3 - maxItems: 3 - clock-names: - items: - - const: aux # Auxiliary (AUX) clock - - const: master_bus # Master AXI clock - - const: slave_bus # Slave AXI clock - resets: - minItems: 12 - maxItems: 12 - reset-names: - items: - - const: axi_m # AXI master reset - - const: axi_s # AXI slave reset - - const: pipe # PIPE reset - - const: axi_m_vmid # VMID reset - - const: axi_s_xpu # XPU reset - - const: parf # PARF reset - - const: phy # PHY reset - - const: axi_m_sticky # AXI sticky reset - - const: pipe_sticky # PIPE sticky reset - - const: pwr # PWR reset - - const: ahb # AHB reset - - const: phy_ahb # PHY AHB reset - - if: properties: compatible: @@ -369,7 +333,6 @@ allOf: contains: enum: - qcom,pcie-apq8064 - - qcom,pcie-ipq4019 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq9574 @@ -428,7 +391,6 @@ allOf: enum: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - - qcom,pcie-ipq4019 - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 then: -- 2.48.1