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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-94888c34c6asm118772939f.10.2025.11.07.11.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 11:16:02 -0800 (PST) From: Alex Elder To: dlan@gentoo.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org Cc: ziyao@disroot.org, aurelien@aurel32.net, johannes@erdfelt.com, mayank.rana@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, shradha.t@samsung.com, inochiama@gmail.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, christian.bruel@foss.st.com, thippeswamy.havalige@amd.com, krishna.chundru@oss.qualcomm.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 0/7] Introduce SpacemiT K1 PCIe phy and host controller Date: Fri, 7 Nov 2025 13:15:49 -0600 Message-ID: <20251107191557.1827677-1-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series introduces a PHY driver and a PCIe driver to support PCIe on the SpacemiT K1 SoC. The PCIe implementation is derived from a Synopsys DesignWare PCIe IP. The PHY driver supports one combination PCIe/USB PHY as well as two PCIe-only PHYs. The combo PHY port uses one PCIe lane, and the other two ports each have two lanes. All PCIe ports operate at 5 GT/second. The PCIe PHYs must be configured using a value that can only be determined using the combo PHY, operating in PCIe mode. To allow that PHY to be used for USB, the needed calibration step is performed by the PHY driver automatically at probe time. Once this step is done, the PHY can be used for either PCIe or USB. This initial version of the driver supports 32 MSIs, and does not support PCI INTx interrupts. The hardware does not support MSI-X. Version 5 of this series incorporates suggestions made during the review of version 4. Specific highlights are detailed below. Note: Aurelien Jarno and Johannes Erdfelt have reported seeing ASPM errors accessing NVMe drives when using earlier versions of this series. The Kconfig files they used were very different from the RISC-V default configuration. Aurelien has since reported the errors do not occur when using defconfig. Johannes has not reported back about this. I do not claim these issues are resolved, however this version of the series does address all other feedback received to date. -Alex This series is available here: https://github.com/riscstar/linux/tree/outgoing/pcie-v5 Between version 3 and version 4: - Clarify that INTx interrupts are not currently supported - Add Rob Herring's Reviewed-by on patch 3 - The name of the PCIe root port will always begin with "pcie" - Lines in the bindings are now wrapped at 80 columns - Subject lines are all captialized (after subsystem tags) - Place the PCIe Kconfig option in the proper location based on vendor name (not Kconfig symbol); expand its description - Drop two PCIe controller Kconfig dependencies - Use dw_pcie_readl_dbi() and dw_pcie_writel_dbi() when turning off ASPM L1 - The dw_pcie_host_ops->init callback has been rearranged a bit: - The vendor and device IDs are now set early - PERST# is asserted separate from putting the controller in RC mode and indicating power is detected - phy_init() is now called later, just before deasserting PERST# - Because of timing issues involved in having the root port enable power, getting and enabling the regulator is back to being done in the PCIe controller probe function - The regulator definition is moved back to the PCIe controller DT node, out of the root port sub-node (in "k1-bananapi-f3.dts") Here is version 4 of this series: https://lore.kernel.org/lkml/20251030220259.1063792-1-elder@riscstar.com/ Between version 3 and version 4: - In the DT binding for the PCIe host controlloller, add a new sub-node representing the root port - Move the phys and supply properties out of the PCIe host controller and into the root port node - Define the spacemit,apmu property later in the binding and DTS files - Define the device_type property first in the binding examples and DTS files - Add root port sub-nodes in the examples and the DTS files - Select the PCI_PWRCTRL_SLOT config option when PCIE_SPACEMIT_K1 is enabled - Parse the root port node in the driver, and get the PHY - Leverage the PCI pwrctrl slot driver to get and enable the regulator - Don't set num_vectors to 256; just use the default (32) - Cleaned up some comments, white space, and symbol names based on feedback from Mani - Add some runtime PM calls to ensure it works propertly - Add a new post_init callback, which disables ASPM L1 for the link Here is version 3 of this series: https://lore.kernel.org/lkml/20251017190740.306780-1-elder@riscstar.com/ Between version 2 and version 3: - Reviewed-by from Rob added to the first two patches - The "num-viewport" property has been removed - The "phy" reset is listed first in the combo PHY binding - The PHY now requires a resets property to specify the "phy" reset - The PCIe driver no longer requires a "phy" reset - The PHY driver now gets and deasserts the reset for all PHYs - Error handling and "put" of clocks in the PHY driver has been corrected (for clk_bulk_get() rather than clk_bulk_get_all()) Here is version 2 of this series: https://lore.kernel.org/lkml/20251013153526.2276556-1-elder@riscstar.com/ Alex Elder (7): dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY dt-bindings: phy: spacemit: Introduce PCIe PHY dt-bindings: pci: spacemit: Introduce PCIe host controller phy: spacemit: Introduce PCIe/combo PHY PCI: spacemit: Add SpacemiT PCIe host driver riscv: dts: spacemit: Add a PCIe regulator riscv: dts: spacemit: PCIe and PHY-related updates .../bindings/pci/spacemit,k1-pcie-host.yaml | 157 ++++ .../bindings/phy/spacemit,k1-combo-phy.yaml | 114 +++ .../bindings/phy/spacemit,k1-pcie-phy.yaml | 71 ++ .../boot/dts/spacemit/k1-bananapi-f3.dts | 44 ++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 + arch/riscv/boot/dts/spacemit/k1.dtsi | 176 +++++ drivers/pci/controller/dwc/Kconfig | 13 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 353 +++++++++ drivers/phy/Kconfig | 11 + drivers/phy/Makefile | 1 + drivers/phy/phy-spacemit-k1-pcie.c | 670 ++++++++++++++++++ 12 files changed, 1644 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml create mode 100644 drivers/pci/controller/dwc/pcie-spacemit-k1.c create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c base-commit: 9c0826a5d9aa4d52206dd89976858457a2a8a7ed -- 2.48.1