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Mon, 17 Nov 2025 10:10:47 -0800 (PST) From: Anand Moon To: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [RFC v1 3/5] PCI: rockchip: Fix Slot Capability Register offset for slot power limit Date: Mon, 17 Nov 2025 23:40:11 +0530 Message-ID: <20251117181023.482138-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251117181023.482138-1-linux.amoon@gmail.com> References: <20251117181023.482138-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit As per 17.6.6.1.32 Slot Capability Register (PCIE_RC_CONFIG_SR) reside at offset 0xd4 within the Root Complex (RC) configuration space, not at the offset of the PCI Express Capability List (0xc0). Following changes corrects the register offset to use PCIE_RC_CONFIG_SR (0xd4) to configure Slot Power Limit value. Signed-off-by: Anand Moon --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++-- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index d51780f4a254..d77403bbb81d 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -271,10 +271,10 @@ static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) power = power / 10; } - status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_SR + PCI_EXP_DEVCAP); status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power); status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_SR + PCI_EXP_DEVCAP); } /** diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index c0ec6c32ea16..4ba07ff3a3cf 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -159,6 +159,7 @@ #define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) #define PCIE_RC_CONFIG_DC (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LC (PCIE_RC_CONFIG_BASE + 0xd0) +#define PCIE_RC_CONFIG_SR (PCIE_RC_CONFIG_BASE + 0xd4) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) -- 2.50.1