From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: "Brian Norris" <briannorris@chromium.org>,
"Bjorn Helgaas" <helgaas@kernel.org>,
"René Rebe" <rene@exactco.de>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
"John Paul Adrian Glaubitz" <glaubitz@physik.fu-berlin.de>,
"Riccardo Mottola" <riccardo.mottola@libero.it>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Mario Limonciello" <mario.limonciello@amd.com>
Subject: Re: [PATCH] PCI: Fix PCI bridges not to go to D3Hot on older RISC systems
Date: Wed, 3 Dec 2025 15:27:43 +0100 [thread overview]
Message-ID: <20251203142743.GD2580184@black.igk.intel.com> (raw)
In-Reply-To: <aS_BYeSApI2XuPcD@wunner.de>
Hi,
On Wed, Dec 03, 2025 at 05:49:37AM +0100, Lukas Wunner wrote:
> [cc += Mika]
>
> On Tue, Dec 02, 2025 at 01:54:00PM -0800, Brian Norris wrote:
> > I wonder if we could take a different approach that helps straddle the
> > uncertain boundary here a bit:
> [...]
> > 2) be less aggressive about default-enabling runtime suspend / D3
> > (i.e., only call pm_runtime_allow() in drivers/pci/pcie/portdrv.c in
> > limited circumstances).
> [...]
> > So instead of portdrv.c calling pm_runtime_allow(), we'd leave that
> > decision to user space (i.e., udev or similar). That will help limit the
> > impact of getting #1 "wrong." And it's possible the bad systems didn't
> > really want aggressive PM anyway, so it's not worth much trouble.
>
> I think runtime PM support in the PCIe port driver was primarily
> motivated by the need to power down Thunderbolt controllers when
> they're not in use.
That and also there are discrete GPUs that can runtime suspend when not in
use.
> A Thunderbolt controller exposes a PCIe switch. Daisy-chained
> Thunderbolt devices are thus visible to the OS as nested switches.
> If we followed the approach you're suggesting, users would have to
> manually allow runtime PM on every Switch Upstream and Downstream Port
> as well as the Root Port and they'd have to do that upon hotplugging
> a device. Yes, yes, users could add a udev rule to allow runtime PM
> automatically by default, but that's exactly the policy we have hardcoded
> in the kernel right now, so why the change?
>
> I expect massive power regressions for users (not least Chromebook
> users) if we made that change.
>
> The discrete Thunderbolt controller in my machine consumes 1.5W
> when nothing is attached. Some laptops have multiple of these.
> Recent CPUs with integrated Thunderbolt/USB4 may fail to transition
> the package to a low power state unless the Thunderbolt ports go
> to D3hot.
>
> So I don't think this approach is a viable option.
I agree. If this is limited to some older RISC machines (based on the
$subject) perhaps this could be solved by adding udev rules to block
runtime PM on those certain ports?
next prev parent reply other threads:[~2025-12-03 14:27 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 16:40 [PATCH] PCI: Fix PCI bridges not to go to D3Hot on older RISC systems René Rebe
2025-12-02 16:54 ` John Paul Adrian Glaubitz
2025-12-02 17:04 ` René Rebe
2025-12-02 18:20 ` PCI bridge window issue (Was: Re: [PATCH] PCI: Fix PCI bridges not to go to D3Hot on older RISC systems) Ilpo Järvinen
2025-12-02 18:29 ` PCI bridge window issue René Rebe
2025-12-02 19:35 ` Ilpo Järvinen
2025-12-06 1:07 ` [PATCH] PCI: Fix PCI bridges not to go to D3Hot on older RISC systems Maciej W. Rozycki
2025-12-06 8:31 ` John Paul Adrian Glaubitz
2025-12-06 10:02 ` René Rebe
[not found] ` <339B5A39-BC20-489A-9969-BF01B4E6AD63@exactco.de>
2025-12-07 14:40 ` Maciej W. Rozycki
2025-12-06 10:14 ` René Rebe
2025-12-07 14:31 ` Maciej W. Rozycki
2025-12-02 17:28 ` Bjorn Helgaas
2025-12-02 17:41 ` René Rebe
2025-12-02 21:54 ` Brian Norris
2025-12-03 4:49 ` Lukas Wunner
2025-12-03 14:27 ` Mika Westerberg [this message]
2025-12-03 14:48 ` René Rebe
2025-12-03 15:22 ` Rafael J. Wysocki
2025-12-03 15:26 ` René Rebe
2025-12-03 17:16 ` Rafael J. Wysocki
2025-12-03 5:15 ` Lukas Wunner
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