From: Jason Gunthorpe <jgg@nvidia.com>
To: Nirmoy Das <nirmoyd@nvidia.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>,
iommu@lists.linux.dev, jammy_huang@aspeedtech.com
Subject: Re: [PATCH] PCI: Add quirk for ASPEED AST1150 bridge to prevent false RID aliasing
Date: Wed, 17 Dec 2025 09:36:58 -0400 [thread overview]
Message-ID: <20251217133658.GL6079@nvidia.com> (raw)
In-Reply-To: <20251217133232.274942-1-nirmoyd@nvidia.com>
On Wed, Dec 17, 2025 at 05:32:32AM -0800, Nirmoy Das wrote:
> ASPEED BMC controllers have VGA and USB functions behind a PCIe-to-PCI
> bridge that causes them to share the same stream ID:
>
> [e0]---00.0-[e1-e2]----00.0-[e2]--+-00.0 ASPEED Graphics Family
> \-02.0 ASPEED USB Controller
>
> Both devices get stream ID 0x5e200 due to bridge aliasing, causing the
> USB controller to be rejected with 'Aliasing StreamID unsupported'.
>
> Per ASPEED, the AST1150 operates in PCI mode where downstream devices
> generate their own distinct Requester IDs. Set
> PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT to stop false alias detection.
This isn't right
Per ASPEED the AST1150 always uses the RID of the downstream and never
replaces it with any other RID. There is no real PCI bus inside the
integrated device.
> Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>
> ---
> drivers/pci/quirks.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
No, please add a new quirk. A downstream PCI device is never the root
of translation.
Jason
next prev parent reply other threads:[~2025-12-17 17:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-17 13:32 [PATCH] PCI: Add quirk for ASPEED AST1150 bridge to prevent false RID aliasing Nirmoy Das
2025-12-17 13:36 ` Jason Gunthorpe [this message]
2025-12-17 13:48 ` Robin Murphy
2025-12-17 15:37 ` Nirmoy Das
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