From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: "Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Robert Moore <robert.moore@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Hanjun Guo <guohanjun@huawei.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Marc Zyngier <maz@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
Lorenzo Pieralisi <lpieralisi@kernel.org>
Subject: [PATCH v2 4/7] PCI/MSI: Make the pci_msi_map_rid_ctlr_node() interface firmware agnostic
Date: Thu, 18 Dec 2025 11:14:30 +0100 [thread overview]
Message-ID: <20251218-gicv5-host-acpi-v2-4-eec76cd1d40b@kernel.org> (raw)
In-Reply-To: <20251218-gicv5-host-acpi-v2-0-eec76cd1d40b@kernel.org>
To support booting with OF and ACPI seamlessly, GIC ITS parent code
requires the PCI/MSI irqdomain layer to implement a function to retrieve
an MSI controller fwnode and map an RID in a firmware agnostic way
(ie pci_msi_map_rid_ctlr_node()).
Convert pci_msi_map_rid_ctlr_node() to an OF agnostic interface
(fwnode_handle based) and update the GIC ITS MSI parent code to reflect
the pci_msi_map_rid_ctlr_node() change.
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Marc Zyngier <maz@kernel.org>
---
drivers/irqchip/irq-gic-its-msi-parent.c | 8 ++++----
drivers/pci/msi/irqdomain.c | 22 +++++++++++++++++-----
include/linux/msi.h | 3 ++-
3 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c
index 12f45228c867..4d1ad1ee005d 100644
--- a/drivers/irqchip/irq-gic-its-msi-parent.c
+++ b/drivers/irqchip/irq-gic-its-msi-parent.c
@@ -104,7 +104,7 @@ static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
int nvec, msi_alloc_info_t *info)
{
- struct device_node *msi_node = NULL;
+ struct fwnode_handle *msi_node = NULL;
struct msi_domain_info *msi_info;
struct pci_dev *pdev;
phys_addr_t pa;
@@ -116,15 +116,15 @@ static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
pdev = to_pci_dev(dev);
- rid = pci_msi_map_rid_ctlr_node(pdev, &msi_node);
+ rid = pci_msi_map_rid_ctlr_node(domain->parent, pdev, &msi_node);
if (!msi_node)
return -ENODEV;
- ret = its_translate_frame_address(msi_node, &pa);
+ ret = its_translate_frame_address(to_of_node(msi_node), &pa);
if (ret)
return -ENODEV;
- of_node_put(msi_node);
+ fwnode_handle_put(msi_node);
/* ITS specific DeviceID */
info->scratchpad[0].ul = rid;
diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c
index a329060287b5..3136341e802c 100644
--- a/drivers/pci/msi/irqdomain.c
+++ b/drivers/pci/msi/irqdomain.c
@@ -376,23 +376,35 @@ u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
}
/**
- * pci_msi_map_rid_ctlr_node - Get the MSI controller node and MSI requester id (RID)
+ * pci_msi_map_rid_ctlr_node - Get the MSI controller fwnode_handle and MSI requester id (RID)
+ * @domain: The interrupt domain
* @pdev: The PCI device
- * @node: Pointer to store the MSI controller device node
+ * @node: Pointer to store the MSI controller fwnode_handle
*
- * Use the firmware data to find the MSI controller node for @pdev.
+ * Use the firmware data to find the MSI controller fwnode_handle for @pdev.
* If found map the RID and initialize @node with it. @node value must
* be set to NULL on entry.
*
* Returns: The RID.
*/
-u32 pci_msi_map_rid_ctlr_node(struct pci_dev *pdev, struct device_node **node)
+u32 pci_msi_map_rid_ctlr_node(struct irq_domain *domain, struct pci_dev *pdev,
+ struct fwnode_handle **node)
{
+ struct device_node *of_node;
u32 rid = pci_dev_id(pdev);
pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
- return of_msi_xlate(&pdev->dev, node, rid);
+ of_node = irq_domain_get_of_node(domain);
+ if (of_node) {
+ struct device_node *msi_ctlr_node = NULL;
+
+ rid = of_msi_xlate(&pdev->dev, &msi_ctlr_node, rid);
+ if (msi_ctlr_node)
+ *node = of_fwnode_handle(msi_ctlr_node);
+ }
+
+ return rid;
}
/**
diff --git a/include/linux/msi.h b/include/linux/msi.h
index 8003e3218c46..8ddb05d5c96a 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -702,7 +702,8 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
void pci_msi_mask_irq(struct irq_data *data);
void pci_msi_unmask_irq(struct irq_data *data);
u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev);
-u32 pci_msi_map_rid_ctlr_node(struct pci_dev *pdev, struct device_node **node);
+u32 pci_msi_map_rid_ctlr_node(struct irq_domain *domain, struct pci_dev *pdev,
+ struct fwnode_handle **node);
struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev);
void pci_msix_prepare_desc(struct irq_domain *domain, msi_alloc_info_t *arg,
struct msi_desc *desc);
--
2.50.1
next prev parent reply other threads:[~2025-12-18 10:15 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-18 10:14 [PATCH v2 0/7] irqchip/gic-v5: Code first ACPI boot support Lorenzo Pieralisi
2025-12-18 10:14 ` [PATCH v2 1/7] ACPICA: Add GICv5 MADT structures Lorenzo Pieralisi
2025-12-18 10:14 ` [PATCH v2 2/7] ACPICA: Add Arm IORT IWB node definitions Lorenzo Pieralisi
2025-12-18 10:14 ` [PATCH v2 3/7] irqdomain: Add parent field to struct irqchip_fwid Lorenzo Pieralisi
2026-01-05 12:01 ` Jonathan Cameron
2026-01-07 8:58 ` Lorenzo Pieralisi
2026-01-07 10:04 ` Jonathan Cameron
2026-01-07 17:31 ` Lorenzo Pieralisi
2026-01-13 9:37 ` Thomas Gleixner
2026-01-13 11:04 ` Lorenzo Pieralisi
2025-12-18 10:14 ` Lorenzo Pieralisi [this message]
2026-01-05 12:21 ` [PATCH v2 4/7] PCI/MSI: Make the pci_msi_map_rid_ctlr_node() interface firmware agnostic Jonathan Cameron
2026-01-07 9:23 ` Lorenzo Pieralisi
2026-01-05 17:35 ` Bjorn Helgaas
2025-12-18 10:14 ` [PATCH v2 5/7] irqchip/gic-v5: Add ACPI IRS probing Lorenzo Pieralisi
2026-01-05 13:24 ` Jonathan Cameron
2026-01-08 16:22 ` Lorenzo Pieralisi
2025-12-18 10:14 ` [PATCH v2 6/7] irqchip/gic-v5: Add ACPI ITS probing Lorenzo Pieralisi
2026-01-05 13:55 ` Jonathan Cameron
2026-01-08 16:13 ` Lorenzo Pieralisi
2025-12-18 10:14 ` [PATCH v2 7/7] irqchip/gic-v5: Add ACPI IWB probing Lorenzo Pieralisi
2026-01-05 15:35 ` Jonathan Cameron
2026-01-08 16:12 ` Lorenzo Pieralisi
2026-01-14 15:56 ` [PATCH v2 0/7] irqchip/gic-v5: Code first ACPI boot support Rafael J. Wysocki
2026-01-14 17:03 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251218-gicv5-host-acpi-v2-4-eec76cd1d40b@kernel.org \
--to=lpieralisi@kernel.org \
--cc=acpica-devel@lists.linux.dev \
--cc=bhelgaas@google.com \
--cc=guohanjun@huawei.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=maz@kernel.org \
--cc=rafael@kernel.org \
--cc=robert.moore@intel.com \
--cc=sudeep.holla@arm.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox