From: Inochi Amaoto <inochiama@gmail.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Han Gao <rabenda.cn@gmail.com>,
Manivannan Sadhasivam <mani@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Yixun Lan <dlan@gentoo.org>, Longbin Li <looong.bin@gmail.com>
Subject: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports
Date: Thu, 25 Dec 2025 18:05:27 +0800 [thread overview]
Message-ID: <20251225100530.1301625-1-inochiama@gmail.com> (raw)
Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enable ASPM on all device tree
platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
and L1 capabilities without supporting it.
Override the L0s and L1 Support advertised in Link Capabilities by the
SG2042/SG2044 Root Ports so we don't try to enable those states.
Inochi Amaoto (2):
PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
drivers/pci/quirks.c | 2 ++
include/linux/pci_ids.h | 2 ++
2 files changed, 4 insertions(+)
--
2.52.0
next reply other threads:[~2025-12-25 10:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-25 10:05 Inochi Amaoto [this message]
2025-12-25 10:05 ` [PATCH 1/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports Inochi Amaoto
2025-12-26 1:24 ` Chen Wang
2025-12-25 10:05 ` [PATCH 2/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] " Inochi Amaoto
2025-12-26 16:30 ` [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe " Bjorn Helgaas
2025-12-29 0:17 ` Chen Wang
2025-12-29 15:11 ` Bjorn Helgaas
2025-12-30 9:45 ` Inochi Amaoto
2025-12-30 10:08 ` Manivannan Sadhasivam
2025-12-30 11:08 ` Inochi Amaoto
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