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Thu, 08 Jan 2026 20:08:27 -0800 (PST) Received: from localhost ([2001:19f0:ac00:4eb8:5400:5ff:fe30:7df3]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f248c239sm12869881c88.9.2026.01.08.20.08.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:08:26 -0800 (PST) From: Inochi Amaoto To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Chen Wang , Inochi Amaoto Cc: Han Gao , linux-pci@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li , Han Gao Subject: [PATCH] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports Date: Fri, 9 Jan 2026 12:07:53 +0800 Message-ID: <20260109040756.731169-1-inochiama@gmail.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") force enable ASPM on all device tree platform, the SG2044 root port breaks as it advertises L0s and L1 capabilities without supporting it. Mask the L0s and L1 Support advertised in Link Capabilities in the LINKCAP register SG2044 Root Ports, so the framework won't try to enable those states. Fixes: 3309df45e6b5 ("riscv: dts: sophgo: sg2044: add PCIe device support for SG2044") Signed-off-by: Inochi Amaoto Tested-by: Han Gao --- Change from original patch: 1. use driver to mask the ASPM advertisement Separate from the folloing patch - https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com --- drivers/pci/controller/dwc/pcie-sophgo.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-sophgo.c b/drivers/pci/controller/dwc/pcie-sophgo.c index ad4baaa34ffa..044088898819 100644 --- a/drivers/pci/controller/dwc/pcie-sophgo.c +++ b/drivers/pci/controller/dwc/pcie-sophgo.c @@ -161,6 +161,22 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *pp) raw_spin_unlock_irqrestore(&pp->lock, flags); } +static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + u32 offset, val; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + dw_pcie_dbi_ro_wr_en(pci); + + val = dw_pcie_readl_dbi(pci, PCI_EXP_LNKCAP + offset); + val &= ~(PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); + dw_pcie_writel_dbi(pci, PCI_EXP_LNKCAP + offset, val); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static int sophgo_pcie_host_init(struct dw_pcie_rp *pp) { int irq; @@ -171,6 +187,8 @@ static int sophgo_pcie_host_init(struct dw_pcie_rp *pp) irq_set_chained_handler_and_data(irq, sophgo_pcie_intx_handler, pp); + sophgo_pcie_disable_l0s_l1(pp); + sophgo_pcie_msi_enable(pp); return 0; -- 2.52.0