[PATCH v3 8/10] cxl: add DVSEC config save/restore

smadhavan
2026-01-16T01:42:36Z

Save and restore CXL DVSEC control registers across reset with
CONFIG_LOCK handling so RWL fields are preserved when locked. This
maintains device policy and capability state across cxl_reset while
avoiding writes to locked fields.

Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
drivers/cxl/pci.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++
include/cxl/pci.h | 15 +++++++
2 files changed, 122 insertions(+)

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 5d2bb4431de3..9a9fab60f1e8 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -1161,6 +1161,113 @@ static int cxl_region_flush_host_cpu_caches(struct device *dev, void *data)
return 0;
}

+/*
+ * CXL DVSEC register save/restore
+ */
+static int cxl_save_dvsec_state(struct pci_dev *pdev,
+ struct cxl_type2_saved_state *state, int dvsec)
+{
+ int rc;
+
+ rc = pci_read_config_word(pdev, dvsec + CXL_DVSEC_CTRL_OFFSET,
+ &state->dvsec_ctrl);
+ if (rc)
+ return rc;
+
+ rc = pci_read_config_word(pdev, dvsec + CXL_DVSEC_CTRL2_OFFSET,
+ &state->dvsec_ctrl2);
+ return rc;
+}
+
+static int cxl_restore_dvsec_state(struct pci_dev *pdev,
+ const struct cxl_type2_saved_state *state,
+ int dvsec, bool config_locked)
+{
+ int rc;
+ u16 val_to_restore;
+
+ if (config_locked) {
+ u16 current_val;
+
+ rc = pci_read_config_word(pdev, dvsec + CXL_DVSEC_CTRL_OFFSET,
+ &current_val);
+ if (rc)
+ return rc;
+
+ val_to_restore = (current_val & CXL_DVSEC_CTRL_RWL_MASK) |
+ (state->dvsec_ctrl & ~CXL_DVSEC_CTRL_RWL_MASK);
+ } else {
+ val_to_restore = state->dvsec_ctrl;
+ }
+
+ rc = pci_write_config_word(pdev, dvsec + CXL_DVSEC_CTRL_OFFSET,
+ val_to_restore);
+ if (rc)
+ return rc;
+
+ rc = pci_write_config_word(pdev, dvsec + CXL_DVSEC_CTRL2_OFFSET,
+ state->dvsec_ctrl2);
+ return rc;
+}
+
+/**
+ * cxl_config_save_state - Save CXL configuration state
+ * @pdev: PCI device
+ * @state: Structure to store saved state
+ *
+ * Saves CXL DVSEC state before reset.
+ */
+int cxl_config_save_state(struct pci_dev *pdev,
+ struct cxl_type2_saved_state *state)
+{
+ struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+ int dvsec;
+
+ if (!cxlds || !state)
+ return -EINVAL;
+
+ memset(state, 0, sizeof(*state));
+
+ dvsec = cxlds->cxl_dvsec;
+ if (!dvsec)
+ return -ENODEV;
+
+ return cxl_save_dvsec_state(pdev, state, dvsec);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_config_save_state, "CXL");
+
+/**
+ * cxl_config_restore_state - Restore CXL configuration state
+ * @pdev: PCI device
+ * @state: Previously saved state
+ *
+ * Restores CXL DVSEC state after reset.
+ */
+int cxl_config_restore_state(struct pci_dev *pdev,
+ const struct cxl_type2_saved_state *state)
+{
+ struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+ bool config_locked;
+ int rc, dvsec;
+ u16 lock_reg;
+
+ if (!cxlds || !state)
+ return -EINVAL;
+
+ dvsec = cxlds->cxl_dvsec;
+ if (!dvsec)
+ return -ENODEV;
+
+ rc = pci_read_config_word(pdev, dvsec + CXL_DVSEC_LOCK_OFFSET, &lock_reg);
+ if (rc)
+ return rc;
+
+ config_locked = !!(lock_reg & CXL_DVSEC_LOCK_CONFIG_LOCK);
+
+ return cxl_restore_dvsec_state(pdev, state, dvsec, config_locked);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_config_restore_state, "CXL");
+
static int cxl_check_region_driver_bound(struct device *dev, void *data)
{
struct cxl_decoder *cxld = to_cxl_decoder(dev);
diff --git a/include/cxl/pci.h b/include/cxl/pci.h
index 71d8de5de948..2c629ded73cc 100644
--- a/include/cxl/pci.h
+++ b/include/cxl/pci.h
@@ -4,6 +4,18 @@
#ifndef __CXL_ACCEL_PCI_H
#define __CXL_ACCEL_PCI_H

+/* CXL Type 2 device state for save/restore across reset */
+struct cxl_type2_saved_state {
+ /* DVSEC registers */
+ u16 dvsec_ctrl;
+ u16 dvsec_ctrl2;
+};
+
+int cxl_config_save_state(struct pci_dev *pdev,
+ struct cxl_type2_saved_state *state);
+int cxl_config_restore_state(struct pci_dev *pdev,
+ const struct cxl_type2_saved_state *state);
+
/*
* See section 8.1 Configuration Space Registers in the CXL 2.0
* Specification. Names are taken straight from the specification with "CXL" and
@@ -23,6 +35,7 @@
#define CXL_DVSEC_CXL_RST_MEM_CLR_CAPABLE BIT(11)
#define CXL_DVSEC_CTRL_OFFSET 0xC
#define CXL_DVSEC_MEM_ENABLE BIT(2)
+#define CXL_DVSEC_CTRL_RWL_MASK 0x5FED
#define CXL_DVSEC_CTRL2_OFFSET 0x10
#define CXL_DVSEC_DISABLE_CACHING BIT(0)
#define CXL_DVSEC_INIT_CACHE_WBI BIT(1)
@@ -32,6 +45,8 @@
#define CXL_DVSEC_CACHE_INVALID BIT(0)
#define CXL_DVSEC_CXL_RST_COMPLETE BIT(1)
#define CXL_DVSEC_CXL_RESET_ERR BIT(2)
+#define CXL_DVSEC_LOCK_OFFSET 0x14
+#define CXL_DVSEC_LOCK_CONFIG_LOCK BIT(0)
#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + ((i) * 0x10))
#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + ((i) * 0x10))
#define CXL_DVSEC_MEM_INFO_VALID BIT(0)
--
2.34.1