[PATCH v3 0/10] CXL reset support for Type 2 devices

smadhavan
2026-01-16T01:42:14Z

Hi folks!

This patch series introduces support for the CXL Reset method for CXL
devices, implementing the reset procedure outlined in CXL Spec [1] v3.2,
Sections 9.6 and 9.7.

v3 changes:
- Restrict CXL reset to Type 2 devices only
- Add host and device cache flushing for
* all sibling functions on multi-function devices
* all sibling devices in a given region
- Add region teardown and memory online detection before reset
- Add configuration state save/restore (DVSEC, HDM, IDE)
- Split the series by subsystem and functional blocks

v2 changes:
- De-duplicate CXL DVSEC register defines under include/cxl/pci.h
- Fix style-related issues

v1 changes:
- Added cover letter and dropped the RFC

The RFC patches can be found here [2]
v2 patches can be found here [3]

Motivation:
-----------
This change is broadly useful for reasons including but not limited to the
following:

- As support for Type 2 devices [4] is being introduced, more devices will
require finer-grained reset mechanisms beyond bus-wide reset methods.

- FLR does not affect CXL.cache or CXL.mem protocols, making CXL Reset
the preferred method in some cases.

- The CXL spec (Sections 7.2.3 Binding and Unbinding, 9.5 FLR) highlights use
cases like function rebinding and error recovery, where CXL Reset is
explicitly mentioned.

Change Description:
-------------------

Patch 1: Move CXL DVSEC defines to the CXL PCI header
- Consolidate DVSEC register definitions under include/cxl/pci.h

Patch 2: Switch PCI CXL port DVSEC defines
- Use the shared CXL PCI header in the PCI core

Patch 3: Add Type 2 helper and reset DVSEC bits
- Add helper to identify Type 2 devices
- Define DVSEC reset/cache control bits

Patch 4: Add the CXL reset method in the PCI core
- Implement cxl_reset() method with capability checks and reset sequence
- Restrict to Type 2 devices

Patch 5: Add reset preparation and region teardown
- Implement region validation and teardown before reset
- Add device cache flush for all sibling devices in a given region

Patch 6: Wire CXL reset prepare/cleanup in PCI
- Call CXL reset prepare/cleanup around the core reset flow

Patch 7: Add host CPU cache flush and multi-function support
- Add host CPU cache flush (x86: wbinvd, arm64: dcache_clean_inval_poc)
- Add device cache flush for all sibling functions on multi-function devices

Patch 8: Add DVSEC configuration state save/restore
- Save/restore DVSEC registers (DEVCTL, DEVCTL2) with CONFIG_LOCK handling

Patch 9: Save/restore CXL config around reset
- Save PCI and CXL config before reset and restore afterwards

Patch 10: Add HDM decoder and IDE state save/restore
- Save/restore HDM decoder and IDE register state

The reset sequence: validate device type, check memory offline, tear down
regions, flush host CPU caches, flush device caches (all functions), save
config state, initiate reset, wait for completion, restore config state.

Command line to test the CXL reset on a capable device:
echo cxl_reset > /sys/bus/pci/devices/<pci_device>/reset_method
echo 1 > /sys/bus/pci/devices/<pci_device>/reset

[1] https://computeexpresslink.org/cxl-specification/
[2] https://lore.kernel.org/all/20241213074143.374-1-smadhavan@nvidia.com/
[3] https://lore.kernel.org/all/20250221043906.1593189-1-smadhavan@nvidia.com/
[4] https://lore.kernel.org/linux-cxl/20251205115248.772945-1-alejandro.lucero-palau@amd.com/

Srirangan Madhavan (10):
[PATCH v3 1/10] cxl: move DVSEC defines to cxl pci header
[PATCH v3 2/10] PCI: switch CXL port DVSEC defines
[PATCH v3 3/10] cxl/pci: add type 2 helper and reset DVSEC bits
[PATCH v3 4/10] PCI: add CXL reset method
[PATCH v3 5/10] cxl/pci: add reset prepare and region teardown
[PATCH v3 6/10] PCI: wire CXL reset prepare/cleanup
[PATCH v3 7/10] cxl/pci: add host cache flush and multi-function reset
[PATCH v3 8/10] cxl/pci: add DVSEC config save/restore
[PATCH v3 9/10] PCI: save/restore CXL config around reset
[PATCH v3 10/10] cxl/pci: add HDM decoder and IDE save/restore

drivers/cxl/core/pci.c | 1 +
drivers/cxl/core/regs.c | 8 +
drivers/cxl/cxl.h | 4 +
drivers/cxl/cxlpci.h | 53 ---
drivers/cxl/pci.c | 621 +++++++++++++++++++++++++++++++++-
drivers/pci/pci.c | 146 +++++++-
include/cxl/pci.h | 134 ++++++++
include/linux/pci.h | 5 +-
include/uapi/linux/pci_regs.h | 5 -
9 files changed, 909 insertions(+), 68 deletions(-)
create mode 100644 include/cxl/pci.h

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2.34.1