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Thu, 15 Jan 2026 17:42:04 -0800 From: To: , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v3 7/10] cxl: add host cache flush and multi-function reset Date: Fri, 16 Jan 2026 01:41:43 +0000 Message-ID: <20260116014146.2149236-8-smadhavan@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260116014146.2149236-1-smadhavan@nvidia.com> References: <20260116014146.2149236-1-smadhavan@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E2:EE_|LV9PR12MB9757:EE_ X-MS-Office365-Filtering-Correlation-Id: 5150774f-cb0e-4d82-eee5-08de54a07d03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8AmUkgxLf1aAhvzUy9ZsX8/sM+IqeFjb333Ii9qRrGXaAAbgXxg0Ryg5FlsU?= =?us-ascii?Q?zAJUa/oJLjoxyU9QTwVyglaHqv7WsvlgwMfz7Jy1gNWf1Tws58UhLIk6RKfJ?= =?us-ascii?Q?UKJ2I2qvxI47JlW04y1VleDH7XyOQAU7qsgmxT9qTSVJ9FtlaLYdoZarqiuO?= =?us-ascii?Q?4Y3+M8yDS0ZFiz5Y3BpvtxW9UHjqhNkRBCSh2ocj6JVJecdhrhu6vDp/8TYI?= =?us-ascii?Q?08Az7hhMoR2Gl/9NfQ8bLgfDCYY0lOvX8Bf8Arocr+SRjX9Ctwysmom5tASK?= =?us-ascii?Q?EYJkCFIY3Vq/hh2PSXvOxf96KDXa6/FbrswLoSs+AB+OHdf5OFox4VLt9PnF?= =?us-ascii?Q?MlSjMuRFIwlTuQ9RQwPZksG5393phQY2/gImdkfavjaGPRBXyyOjTHBk0CGJ?= =?us-ascii?Q?HR5CmCOyG6INse34SFvH489YLI20rzM+AN+HMShgKZG3Wawpqjf5lOncXrJP?= =?us-ascii?Q?36nwAQpfmmND29SOLDgnC46IycMaT0Bp3lErIHHdUEW/h4S/d4Gz5OLitGbG?= =?us-ascii?Q?2OlInETC/vk0exDrn6UmJQrcVCCFGwZUomW+mSmB89O8KWPfqNBQTivLl9Rh?= =?us-ascii?Q?cUf63egoUWmhx5hFL30MzMH9TPxXPq5yfwmzFq+Jrvq3EbZbq/pHvFYFThWz?= =?us-ascii?Q?qRlUEyxDrYg1F2Gz4XFSRDRw1BetpOjfO8/s1UfkqGOW7FYrkRHLOSLJfqok?= =?us-ascii?Q?okqHG/RXO4QvSTffFQJYoabK5Q3qZHXihp6G2wWKnYI+HR+zSjy8dWZF40El?= =?us-ascii?Q?fUil6pyKNgbOOebgJYWdLTbTncKgvzPAElVKLcUP2kgmzZdscACtXpGnRaLX?= =?us-ascii?Q?/UztLdCAHuehASJHdkDY2RYw+tiqSwVfP0KZXIVIMrDLZOLkwc7xu5Nr1VpL?= =?us-ascii?Q?izf/7mLyy347MexhxKDh9zddwf21iYJgzsTn91PlOY75fSTSWBqUkH+fprbK?= =?us-ascii?Q?5podqszRiOLt3YUQcw/2EO1OAdn1vRNsAIqSwCImXfDMx9ggTBq3QvaLQJox?= =?us-ascii?Q?ouFv4rHR4se5ye2G0lKO2Nm4SZ/6jxRvZOJ9DGg+7HdqlKFYGW694k0CVhNI?= =?us-ascii?Q?PcsjMCf0GBQTvSpr3YS/MmY6Vv/h8KDdasCusZCs+BRwHlJ0GtpnC495TlmI?= =?us-ascii?Q?nr/YeKgt/Q63E8U7e+sVL404LZiL8k60kYYmd4wH8/ed/tB/2AMD9DA5o0lD?= =?us-ascii?Q?5znW/wDetAws9QeQeOEq9igsL0UuUEJtphWokqU3RliU/8EEZPmtTYXfz8X6?= =?us-ascii?Q?6uThLekx3qY6ujaohcQJAWHL4kpE5gpj4/b2IJ5RPYb+weMESMsBJUj92ah9?= =?us-ascii?Q?5kNopamA/DZsJ8JJztvxEN15TCCO7PxLo6zQ+pEMeSBXfmIBM/FBRWwCWmNy?= =?us-ascii?Q?VXIQbSiQGiO+ubK8KeLiptHKTbjVZk/Ygj6aoZyn/g/YMmMh/RmcfkRm3FUs?= =?us-ascii?Q?MwOiBBKjrrKfgSQNEz840FiAVMHd1RYQEjI0EoEyHClgjb331RNryvo/H9ND?= =?us-ascii?Q?pyBzTGYYtTWpNs+HtzQBnnYwHH/zeLkJDwo22x0SGvITPrBGpNj+ctezKIL6?= =?us-ascii?Q?5vGhqSu9UMB8iV7FnZYHMMrhMIP7tq6LO5Ugt4vvk/IlHxCvKVXMdKubRiDF?= =?us-ascii?Q?3NvyXpZ7RW6GDiaMd8BdJYpZcReIutNuKytQjSI+5HhLkNtEFpopYd93HWFa?= =?us-ascii?Q?wBhtZiWVwa9YCdk9DLI/Up2xgws=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2026 01:42:20.0307 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5150774f-cb0e-4d82-eee5-08de54a07d03 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9757 From: Srirangan Madhavan Flush host CPU caches for mapped HDM ranges after teardown and prepare sibling Type 2 functions on multi-function devices. The host cache maintenance uses wbinvd_on_all_cpus() on x86 and VA-based PoC clean+ invalidate on arm64 via memremap() and on_each_cpu(), matching the required ordering before reset. Signed-off-by: Srirangan Madhavan --- drivers/cxl/pci.c | 150 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 148 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 8da69c2125af..5d2bb4431de3 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -11,6 +11,10 @@ #include #include #include +#include +#include +#include +#include #include #include #include "cxlmem.h" @@ -1092,6 +1096,71 @@ bool cxl_is_type2_device(struct pci_dev *pdev) return cxlds->type == CXL_DEVTYPE_DEVMEM; } +#ifdef CONFIG_ARM64 +struct cxl_cache_flush_ctx { + void *va; + size_t len; +}; + +static void cxl_flush_by_va_local(void *info) +{ + struct cxl_cache_flush_ctx *ctx = info; + + dcache_clean_inval_poc((unsigned long)ctx->va, + (unsigned long)ctx->va + ctx->len); + asm volatile("dsb ish" ::: "memory"); +} +#endif + +static int cxl_region_flush_host_cpu_caches(struct device *dev, void *data) +{ + struct cxl_endpoint_decoder *cxled = to_cxl_endpoint_decoder(dev); + struct cxl_region *cxlr = cxled->cxld.region; + struct resource *res; + + if (!is_endpoint_decoder(dev)) + return 0; + + if (!cxlr || !cxlr->params.res) + return 0; + + res = cxlr->params.res; + +#ifdef CONFIG_X86 + static bool flushed; + + if (!flushed) { + wbinvd_on_all_cpus(); + flushed = true; + } +#elif defined(CONFIG_ARM64) + void *va; + size_t len, line_size = L1_CACHE_BYTES; + phys_addr_t start, end, aligned_start, aligned_end; + struct cxl_cache_flush_ctx flush_ctx; + + start = res->start; + end = res->end; + + aligned_start = ALIGN_DOWN(start, line_size); + aligned_end = ALIGN(end + 1, line_size); + len = aligned_end - aligned_start; + + va = memremap(aligned_start, len, MEMREMAP_WB); + if (!va) { + pr_warn("Failed to map region for cache flush\n"); + return 0; + } + + flush_ctx.va = va; + flush_ctx.len = len; + on_each_cpu(cxl_flush_by_va_local, &flush_ctx, 1); + + memunmap(va); +#endif + return 0; +} + static int cxl_check_region_driver_bound(struct device *dev, void *data) { struct cxl_decoder *cxld = to_cxl_decoder(dev); @@ -1252,6 +1321,9 @@ static int cxl_reset_prepare_memdev(struct pci_dev *pdev) return rc; } + device_for_each_child(&endpoint->dev, NULL, + cxl_region_flush_host_cpu_caches); + /* Keep cxl_region_rwsem held, released by cleanup function */ return 0; } @@ -1266,12 +1338,79 @@ static void cxl_reset_cleanup_memdev(struct pci_dev *pdev) up_write(&cxl_region_rwsem); } +static int cxl_reset_prepare_all_functions(struct pci_dev *pdev) +{ + struct pci_dev *func_dev; + unsigned int devfn; + int func, rc; + struct pci_dev *prepared_funcs[8] = { NULL }; + int prepared_count = 0; + + for (func = 0; func < 8; func++) { + devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), func); + + if (devfn == pdev->devfn) + continue; + + func_dev = pci_get_slot(pdev->bus, devfn); + if (!func_dev) + continue; + + if (!cxl_is_type2_device(func_dev)) { + pci_dev_put(func_dev); + continue; + } + + rc = cxl_reset_prepare_memdev(func_dev); + if (rc) { + pci_dev_put(func_dev); + goto cleanup_funcs; + } + + prepared_funcs[prepared_count++] = func_dev; + } + + return 0; + +cleanup_funcs: + for (func = 0; func < prepared_count; func++) { + if (prepared_funcs[func]) { + cxl_reset_cleanup_memdev(prepared_funcs[func]); + pci_dev_put(prepared_funcs[func]); + } + } + return rc; +} + +static void cxl_reset_cleanup_all_functions(struct pci_dev *pdev) +{ + struct pci_dev *func_dev; + unsigned int devfn; + int func; + + for (func = 0; func < 8; func++) { + devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), func); + + if (devfn == pdev->devfn) + continue; + + func_dev = pci_get_slot(pdev->bus, devfn); + if (!func_dev) + continue; + + if (cxl_is_type2_device(func_dev)) + cxl_reset_cleanup_memdev(func_dev); + + pci_dev_put(func_dev); + } +} + /** * cxl_reset_prepare_device - Prepare CXL device for reset * @pdev: PCI device being reset * * CXL-reset-specific preparation. Validates memory is offline, flushes - * device caches, and tears down regions. + * device caches, and tears down regions for device and siblings. * * Returns: 0 on success, -EBUSY if memory online, negative on error */ @@ -1290,6 +1429,12 @@ int cxl_reset_prepare_device(struct pci_dev *pdev) return rc; } + rc = cxl_reset_prepare_all_functions(pdev); + if (rc) { + cxl_reset_cleanup_memdev(pdev); + return rc; + } + return 0; } EXPORT_SYMBOL_NS_GPL(cxl_reset_prepare_device, "CXL"); @@ -1298,10 +1443,11 @@ EXPORT_SYMBOL_NS_GPL(cxl_reset_prepare_device, "CXL"); * cxl_reset_cleanup_device - Cleanup after CXL reset * @pdev: PCI device that was reset * - * Releases region locks held during reset. + * Releases region locks for device and all sibling functions. */ void cxl_reset_cleanup_device(struct pci_dev *pdev) { + cxl_reset_cleanup_all_functions(pdev); cxl_reset_cleanup_memdev(pdev); } EXPORT_SYMBOL_NS_GPL(cxl_reset_cleanup_device, "CXL"); -- 2.34.1