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Tue, 20 Jan 2026 14:26:26 -0800 From: To: , , , , , , , , , , , , , CC: , , , , , , , kernel test robot Subject: [PATCH v4 04/10] PCI: add CXL reset method Date: Tue, 20 Jan 2026 22:26:04 +0000 Message-ID: <20260120222610.2227109-5-smadhavan@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120222610.2227109-1-smadhavan@nvidia.com> References: <20260120222610.2227109-1-smadhavan@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001504:EE_|DS0PR12MB8415:EE_ X-MS-Office365-Filtering-Correlation-Id: 034d2cc9-c1a1-4b2d-e350-08de5872ffd4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?kf3AP47jsHsZl99PgHvmVswwXSuQHELk3bhUszuoJKKodynCcvXljYQ1Rbkm?= =?us-ascii?Q?/C7Q6QfipJqhPccS2qkAIkGUgXDJ6nKsEaLMJ1+aqVOF4Cimo1R/+YBK37lk?= =?us-ascii?Q?xEdOhBzKJ16wNDqOcjMu8HBAcVrFIlTaGdhI/gDzgRJMOOOzTd7ac9e8Ei0/?= =?us-ascii?Q?04BBWcZtrE21rTeGiy83XoEr9EsdEfyUY6vXlFJjjyREIlCzhunoSEcGQx1E?= =?us-ascii?Q?jcaeLftfjwdQD6hIsgLH6zfxHN3OetNwwLwBHKFQas+KlRiADbT3jUnNi6HR?= =?us-ascii?Q?FCi12aJu/WAxHtehdJIIX3kYx5mr1vp1rzGQqozN5RxUHMG4jEqWle5vZfAu?= =?us-ascii?Q?1L38SVAAKp4lf4ljyVRJ4lIQObTTe7gDqGkvPhEFjBc5m6r4BPyL6Z/9IuFL?= =?us-ascii?Q?mu6rKCDRPldlF72t/DZlVJz5bUqQDVxk20eU9i2/wGztl2zp+SJCwBuiYEKO?= =?us-ascii?Q?bWrW1NCcsGCNXPwoHpgwRQ1ZIx3dRs20L5h3eYOL5stmB1J2TVkrvcGcCOaE?= =?us-ascii?Q?Vjw1IZIklA8gxRGlxzgMQRvtl6fh8iXQkP9lN9EB32XI0vzENRr8yQZcBc4L?= =?us-ascii?Q?CZt92y8xogIL/roPfES9CbqPqpZAW1HqKMJd8F9eCkA/UW6tT8XU2GzlGW2t?= =?us-ascii?Q?ZTbGYZWqnTgT3x4RMC33HLrxmDM3pSNkvBDU0zZy8AOZortexYYNArgnhZ7f?= =?us-ascii?Q?H5rWzf/fhZLzM6ZlCfFgymaypfwXAg963EGUCUmI5IWcO1r9ea6002PkxL3K?= =?us-ascii?Q?bMWWoToCNHpPaw3tUka861n7lXSDUI8zSq4mdG17PyJxpum2fZPmifQjr7c8?= =?us-ascii?Q?VnyiCnhA9ZU5A1kv4Rnuj0toC0c6izeYJuF4YWVr2QEu9TTiOBN1O8X3G57R?= =?us-ascii?Q?Y6b0vaKaEC7b5orZoaifOrsX3Gb7eoex9d1+DssdFYmoMl4CoQMMOdnJ7g9h?= =?us-ascii?Q?MLLQSrnWaMe1ql0leXgSrGgdaDPN/e7WdD1aAVWx+OJ0qjogkXh7Sm/UbzqN?= =?us-ascii?Q?cmshC0nDll4lAYwzGROEEv5Js0j26iZG3te55DN2AJ+h8iGbB6oWibSENQC/?= =?us-ascii?Q?fp+RY47cR+q4+e6bYPsAANJ4qazxJu3TV1ViMz8NitdFeQCbUBa03U4YrXOS?= =?us-ascii?Q?zv6JO1i0IMII++2+XFoJzdJogvhIzSYIYFQhtr24t/JkcGXbHdBnNU9kN8Px?= =?us-ascii?Q?7+7ecOinohsa4t+/rDfTZUl/dtjEe4v9yqTKff6SaoQChRkQA4bOHfWUYUuE?= =?us-ascii?Q?5WltyoSX/t2OI+fg4AKNC7jS3hAyUz5GDZFZwUE5Lo1j/kh40j5Ifsz/2+NY?= =?us-ascii?Q?8fPoq4+IGn7vYt5/b7sB9RyBxg456alJLnWAznV0qZ5mjdDLiLVG9cCMEVhM?= =?us-ascii?Q?zADnWSbNX3zT5ACP3I9RSzDGQweVcHAzKz62TWd3NMzSCDI+qzCVmKDlXHbF?= =?us-ascii?Q?L1Nh3RXq3oUL7kAR8xGzACZk6z4hFprfhWi4bFBu+7U1dj+dmsbGQjbkxSIQ?= =?us-ascii?Q?d9EJeVQolcsrR56cxFOdkuZD4P+O9Kc3jX7xWl/nYZa3b4jMbE++AoJR/ms2?= =?us-ascii?Q?2yBhuXOhhwkF9wqqFsQLOsqYnt6+mbVlUOdkKOJeNFhYJGrtP9A61Of1LVEH?= =?us-ascii?Q?d1SF0sPMtp/7SjjjADkMceWZ1iWFsl+c5vk+xnKAcA9jz/YIIzRNBLpeD8k3?= =?us-ascii?Q?+2rC0mqwmNS66lxiw5Oj4nwuv28=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 22:26:47.3272 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 034d2cc9-c1a1-4b2d-e350-08de5872ffd4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001504.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8415 From: Srirangan Madhavan Add a PCI reset method "cxl_reset" that drives the CXL reset sequence using DVSEC controls and timeout encoding. The method is restricted to Type 2 devices, limiting the scope of the changes. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202601172246.rz4Orygn-lkp@intel.com/ Signed-off-by: Srirangan Madhavan --- drivers/pci/pci.c | 104 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 10 ++++- 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8bb07e253646..e2d5ff25ab67 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4892,6 +4892,109 @@ static int pci_reset_bus_function(struct pci_dev *dev, bool probe) return pci_parent_bus_reset(dev, probe); } +static int cxl_reset_init(struct pci_dev *dev, u16 dvsec) +{ + /* + * Timeout values ref CXL Spec v3.2 Ch 8 Control and Status Registers, + * under section 8.1.3.1 DVSEC CXL Capability. + */ + u32 reset_timeouts_ms[] = { 10, 100, 1000, 10000, 100000 }; + u16 reg; + u32 timeout_ms; + int rc, ind; + + /* Check if CXL Reset MEM CLR is supported. */ + rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_CAP_OFFSET, ®); + if (rc) + return rc; + + if (reg & CXL_DVSEC_CXL_RST_MEM_CLR_CAPABLE) { + rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_CTRL2_OFFSET, + ®); + if (rc) + return rc; + + reg |= CXL_DVSEC_CXL_RST_MEM_CLR_ENABLE; + pci_write_config_word(dev, dvsec + CXL_DVSEC_CTRL2_OFFSET, reg); + } + + /* Read timeout value. */ + rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_CAP_OFFSET, ®); + if (rc) + return rc; + ind = FIELD_GET(CXL_DVSEC_CXL_RST_TIMEOUT_MASK, reg); + timeout_ms = reset_timeouts_ms[ind]; + + /* Write reset config. */ + rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_CTRL2_OFFSET, ®); + if (rc) + return rc; + + reg |= CXL_DVSEC_INIT_CXL_RESET; + pci_write_config_word(dev, dvsec + CXL_DVSEC_CTRL2_OFFSET, reg); + + /* Wait till timeout and then check reset status is complete. */ + msleep(timeout_ms); + rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_STATUS2_OFFSET, ®); + if (rc) + return rc; + if (reg & CXL_DVSEC_CXL_RESET_ERR || + ~reg & CXL_DVSEC_CXL_RST_COMPLETE) + return -ETIMEDOUT; + + rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_CTRL2_OFFSET, ®); + if (rc) + return rc; + reg &= (~CXL_DVSEC_DISABLE_CACHING); + pci_write_config_word(dev, dvsec + CXL_DVSEC_CTRL2_OFFSET, reg); + + return 0; +} + +/** + * cxl_reset - initiate a cxl reset + * @dev: device to reset + * @probe: if true, return 0 if device can be reset this way + * + * Initiate a cxl reset on @dev. + */ +static int cxl_reset(struct pci_dev *dev, bool probe) +{ + u16 dvsec, reg; + int rc; + + dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + CXL_DVSEC_PCIE_DEVICE); + if (!dvsec) + return -ENOTTY; + + /* Check if CXL Reset is supported. */ + rc = pci_read_config_word(dev, dvsec + CXL_DVSEC_CAP_OFFSET, ®); + if (rc) + return -ENOTTY; + + if ((reg & CXL_DVSEC_CXL_RST_CAPABLE) == 0) + return -ENOTTY; + +#if !IS_REACHABLE(CONFIG_CXL_PCI) + return -ENOTTY; +#endif + + /* + * Expose CXL reset for Type 2 devices. + */ + if (!cxl_is_type2_device(dev)) + return -ENOTTY; + + if (probe) + return 0; + + if (!pci_wait_for_pending_transaction(dev)) + pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); + + return cxl_reset_init(dev, dvsec); +} + static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) { struct pci_dev *bridge; @@ -5016,6 +5119,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods[] = { { pci_dev_acpi_reset, .name = "acpi" }, { pcie_reset_flr, .name = "flr" }, { pci_af_flr, .name = "af_flr" }, + { cxl_reset, .name = "cxl_reset" }, { pci_pm_reset, .name = "pm" }, { pci_reset_bus_function, .name = "bus" }, { cxl_reset_bus_function, .name = "cxl_bus" }, diff --git a/include/linux/pci.h b/include/linux/pci.h index 864775651c6f..4a8c4767db6e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -51,7 +51,7 @@ PCI_STATUS_PARITY) /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ -#define PCI_NUM_RESET_METHODS 8 +#define PCI_NUM_RESET_METHODS 9 #define PCI_RESET_PROBE true #define PCI_RESET_DO_RESET false @@ -1464,6 +1464,14 @@ int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, int pci_select_bars(struct pci_dev *dev, unsigned long flags); bool pci_device_is_present(struct pci_dev *pdev); +#ifdef CONFIG_CXL_PCI +bool cxl_is_type2_device(struct pci_dev *dev); +#else +static inline bool cxl_is_type2_device(struct pci_dev *dev) +{ + return false; +} +#endif void pci_ignore_hotplug(struct pci_dev *dev); struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); int pci_status_get_and_clear_errors(struct pci_dev *pdev); -- 2.34.1