Re: [PATCH v4 03/10] cxl: add type 2 helper and reset DVSEC bits

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Tue, 20 Jan 2026 16:27:33 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> On 1/20/26 3:26 PM, smadhavan@nvidia.com wrote:
> > From: Srirangan Madhavan <smadhavan@nvidia.com>
> > 
> > Introduce a helper to identify CXL Type 2 devices and define the DVSEC
> > reset/cache control bits used by the reset flow.  
> 
> Should probably be 2 separate patches for these 2 things.

Also, follow existing convention and put them new DVSEC defs
in the uapi/pci_regs.h file.  The rest are moving there shortly.

Given they are now in a uapi file, I also wonder if we should just
fill in the rest of the structure definitions as a stand alone
patch.  A partial set isn't much use to userspace tooling.

Jonathan

> 
> > 
> > Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> > ---
> >  drivers/cxl/pci.c | 10 ++++++++++
> >  include/cxl/pci.h | 14 ++++++++++++++
> >  2 files changed, 24 insertions(+)
> > 
> > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> > index 55c767df4543..b562e607ec46 100644
> > --- a/drivers/cxl/pci.c
> > +++ b/drivers/cxl/pci.c
> > @@ -1075,6 +1075,16 @@ static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev)
> >  	return PCI_ERS_RESULT_RECOVERED;
> >  }
> > 
> > +bool cxl_is_type2_device(struct pci_dev *pdev)
> > +{
> > +	struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> > +
> > +	if (!cxlds)
> > +		return false;
> > +
> > +	return cxlds->type == CXL_DEVTYPE_DEVMEM;
> > +}
> > +
> >  static void cxl_error_resume(struct pci_dev *pdev)
> >  {
> >  	struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> > diff --git a/include/cxl/pci.h b/include/cxl/pci.h
> > index 728ba0cdd289..71d8de5de948 100644
> > --- a/include/cxl/pci.h
> > +++ b/include/cxl/pci.h
> > @@ -14,10 +14,24 @@
> >  /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
> >  #define CXL_DVSEC_PCIE_DEVICE					0
> >  #define   CXL_DVSEC_CAP_OFFSET		0xA
> > +#define     CXL_DVSEC_CACHE_CAPABLE	BIT(0)
> >  #define     CXL_DVSEC_MEM_CAPABLE	BIT(2)
> >  #define     CXL_DVSEC_HDM_COUNT_MASK	GENMASK(5, 4)
> > +#define     CXL_DVSEC_CACHE_WBI_CAPABLE	BIT(6)
> > +#define     CXL_DVSEC_CXL_RST_CAPABLE	BIT(7)
> > +#define     CXL_DVSEC_CXL_RST_TIMEOUT_MASK	GENMASK(10, 8)
> > +#define     CXL_DVSEC_CXL_RST_MEM_CLR_CAPABLE	BIT(11)
> >  #define   CXL_DVSEC_CTRL_OFFSET		0xC
> >  #define     CXL_DVSEC_MEM_ENABLE	BIT(2)
> > +#define   CXL_DVSEC_CTRL2_OFFSET	0x10
> > +#define     CXL_DVSEC_DISABLE_CACHING	BIT(0)
> > +#define     CXL_DVSEC_INIT_CACHE_WBI	BIT(1)
> > +#define     CXL_DVSEC_INIT_CXL_RESET	BIT(2)
> > +#define     CXL_DVSEC_CXL_RST_MEM_CLR_ENABLE	BIT(3)
> > +#define   CXL_DVSEC_STATUS2_OFFSET	0x12
> > +#define     CXL_DVSEC_CACHE_INVALID	BIT(0)
> > +#define     CXL_DVSEC_CXL_RST_COMPLETE	BIT(1)
> > +#define     CXL_DVSEC_CXL_RESET_ERR	BIT(2)
> >  #define   CXL_DVSEC_RANGE_SIZE_HIGH(i)	(0x18 + ((i) * 0x10))
> >  #define   CXL_DVSEC_RANGE_SIZE_LOW(i)	(0x1C + ((i) * 0x10))
> >  #define     CXL_DVSEC_MEM_INFO_VALID	BIT(0)  
> 
> Should this chunk go with a different patch where the definitions are being used?
> 
> > --
> > 2.34.1
> >   
> 
>