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Wed, 21 Jan 2026 06:23:57 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH v11 0/5] rust: pci: add config space read/write support Date: Wed, 21 Jan 2026 16:23:49 +0200 Message-ID: <20260121142355.4761-1-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075EF:EE_|SJ2PR12MB7845:EE_ X-MS-Office365-Filtering-Correlation-Id: dcbf9e3b-22c2-45a3-7600-08de58f8c606 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KyGwSV3AYLSJZJMYX0g329s+9jGXiHQdgz/pmwwM8CcA5dH5Ad/fShXz3h+o?= =?us-ascii?Q?hkBBN5W8izZtLSW0MkeIA/IaM8dvQf/OxXq1uy3FSwBYh1afgmxFCHLCCoEi?= =?us-ascii?Q?GgN/VYrAIz/egRTtFqmFo2ZI/INqBcb9OpN3Sp/sWINfO20dWWejGo4rfxqg?= =?us-ascii?Q?CaQ1Lo0Gyn0PLmILNj8wKdQ7mpg4o2W++7IMTBvshqNFYMfW0/9TKIgXJquI?= =?us-ascii?Q?I+u7dxPBlQvJ7TRkO4qs4atjriJ6GY9nlY4Ajb9mLABxts2sGL0bXYNWYOPN?= =?us-ascii?Q?Qftd3NTMlSV79koAlyBoJz4cGpOjbasLp+FQDozXNL9YR41UvZg3EimWd/Yc?= =?us-ascii?Q?F47wOXYs+vq6N4zkrPxlEG700U85jH1u5c5LzSAXPtguUqgta+UFd14YqORP?= =?us-ascii?Q?K1+OZM1q1xx7BWd+2Q36xep0ziZdOuVOEcL2V/QzUjJPWIBxzCjjdfTfXbe6?= =?us-ascii?Q?AfFfm8PLlJB63sSaIXB+HUGzpKjcUhuSjdFBQWV3RAGJ0MfJPhcFj9BmXSzQ?= =?us-ascii?Q?4UUAHw5nuMYX65prLthasJJDTauJPASUrBbT1yyQvLnEn5ErM1RPvPOxKzav?= =?us-ascii?Q?udWeHMuhbVwfhOB4o0I0xReDZssofLPQR0mGRYryoAZ+yWOW3W4yHF+KDZgy?= =?us-ascii?Q?rm9sGsOGwtSC+JCxyjZg1P6Q5FAY98qhPMc3/UmeShk4CpYeAlkS/Mwhfbcc?= =?us-ascii?Q?OXWmhENGuzqqakHMaaQysy8VFe3nAac+3VCpDATpM9L5RpWWsmBuxnN9og9g?= =?us-ascii?Q?7S0K7/myytK4mLAmLOnxt1s1gZTcno2Ww2ckTjWlsvMmEXJknqgtURx0ShSq?= =?us-ascii?Q?dxAD68F9k7VRMRgo9qI78xISg+Tl5XgOBbS2qJpLIAU2ilFs8lhCSTQ1I571?= =?us-ascii?Q?2auUjMbfqwkt+mErqqLfL/vUlZMwdlJCVOWbsg8XB/Wf/lfYBjVsgRjkMxwx?= =?us-ascii?Q?5LVYY1nITBy6yJa6qLrTlRHL/OcI6gDP3TKEQ3HL91nX59uZ4G5YuW5sbkrr?= =?us-ascii?Q?9it9XK9tud+PyRV0yxOoQ6dkyxlQcrsPXGn6RIopk5IK6OHoRivGnB99Rrgf?= =?us-ascii?Q?tsiY2OmC92Ks8ortlmTVIsNEQoK5WizBuuW3O/ESyhajwDd9aQTLpDzedXZE?= =?us-ascii?Q?ENNd9zIrJgTXMjmSG6woMVQOSBRJjImUx1XB+WuxePPqH5H/L/dLlkwlouRP?= =?us-ascii?Q?URvp1mmJGiCx923SehO9Ut3VAJlW7KPWci7DOsk2sCNaKlKevIM92xVbF5Up?= =?us-ascii?Q?mBAKQZEsOg9wrmjfUEbho/wPNQgoUQOkwKBIFK892lNX95oC6PYMdzb231pn?= =?us-ascii?Q?bRTkOCnftzLpMyr/baH8piyXo6z/b7pijXKBJNroz+ogFAwhp+lpRJQ9GwIS?= =?us-ascii?Q?VkoXy/I+/Y7YaZX9eoqvn2pdLdgL/g5QUHay5M8i/+RtPtWxKTxszjD3+Mve?= =?us-ascii?Q?ZUtmEfwkqROK1mPXwysCcAEnkBNdMNvx3I9AM1IirqEPU5pt3gu7O/gIWHU5?= =?us-ascii?Q?VF86bCdxapu/fhCzFIA92ePdBPsmdO9eWTHkiqkcwrCVKbYJFvkgGhy/bGWJ?= =?us-ascii?Q?2ej+NzxvhvP5eTLd5FccO0Ys4SsBEhXewTrkiAaumsqsj3d6Ckk70c3sy25w?= =?us-ascii?Q?taKM4HxHA97ntY/Ba4O8FM1zdXyXuqTTn7Vwv8mA25wF9Plrz9e0tr6VNuRN?= =?us-ascii?Q?Iq6Aj250s6E+jObfeuJfdfFg1Vs=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 14:24:22.9784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dcbf9e3b-22c2-45a3-7600-08de58f8c606 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7845 In the NVIDIA vGPU RFC [1], the PCI configuration space access is required in nova-core for preparing gspVFInfo when vGPU support is enabled. This series is the following up of the discussion with Danilo for how to introduce support of PCI configuration space access in Rust PCI abstractions. Alice/Alex/I had a discussion of the next steps of this patch series in LPC 2025. We agreed that first introducing the functionality before the BoundedInteger work and other refinement is settled. [2] The repo with the patches can be found at [3]. v11: I tried to combine IoCapable and IoTryCapable. I found I have to dump the original forwarding call scheme. In this re-spin, I moved the accessors into the Io/IoKnownSize traits and I have to added the default trait functions required by the compiler. The IoCapable turns into a pure marker trait. Reaching the accessors from a driver are restricted by the where statements marked by IoCapable. A backend marks its capablities via implementing IoCapable. This is quite close to Gary's orginal suggestions. I also left a assert in the default trait functions (accessors) to catch the case that a backend implements IoCapable to claim it support the accessors but forgets to implement the accessors. This should be helpful when developing a new backend. - Combine IoCapable and IoTryCapable. (Danilo/Gary) - Keep IoKnownSize trait. (Alice/Gary) - Fix the compiling error in pwm_th1520 driver. v10: - Merge IoBase trait into Io trait to simplify trait hierarchy. - Use IoCapable and IoTryCapable functional traits (not marker traits) to separate infallible and fallible I/O operations. (Danilo/Gary) I tried implementing the marker traits idea, but I found that the compiler still requires a default implementation for each function in the main trait to avoid forcing backends to implement unsupported methods. However, Gary's core idea of "capabilities" is extremely valuable. So, I adopted a dispatching pattern: - All I/O accessors are defined in the Io trait. They use default implementations to dispatch calls to the underlying IoCapable and IoTryCapable traits. This addresses Alice's concern about the complicated trait hierarchy. It preserves strict compile-time static checks. The compiler can catch the case if a driver calls an accessor not implemented by a backend. - The actual logic resides in IoCapable and IoTryCapable. Backends can selectively implement IoCapable or IoTryCapable based on hardware support. This addresses Markus's concern regarding backends with limited access sizes (e.g., I2C). For example, the Mmio backend implements both IoCapable and IoTryCapable for all sizes, while the PCI config space backend only implements IoCapable for u8/u16/u32. v9: - Rebase the patches to the latest driver-core-testing. - Move ConfigSpaceSize to pci/io.rs. (Danilo) - Refine docs. (Danilo) - Compiling test on Tyr. (Danilo) v8: - Rebase to latest driver-core-testing branch. - Refinement of traits name and hierarchy: (Alice) * Rename IoInfallible trait to IoKnownSize trait. * Keep Infallible helpers in Io trait. v7: - Rebase to latest driver-core-testing branch. - Introduce Io64 trait. (Alice) - Add docs for call_{mmio, config}_{read, write}() macros. (Alex) - Improve the define_{read, write} macros. (Alex) - Add SAFETY/CAST in call_config_{read, write}. (Joel) - Fix typo of method name. (Alex/Joel) v6: - Implement config_space() and config_space_extended() in device::Bound lifecycle. (Danilo) - Fix the "use" in the comment for generating proper rust docs, verify the output of rustdoc. (Miguel) - Improve the comments of PCI configuration space when checking the output of rustdoc. v5: - Remove fallible accessors of PCI configuration space. (Danilo) - Add #[repr(usize)] for enum ConfigSpace. (Danilo) - Refine the handling of return value in read accessors. (Danilo) - Add debug_assert!() in pdev::cfg_size(). (Danilo) - Add ConfigSpace.as_raw() for extracting the raw value. (Danilo) - Rebase the patches on top of driver-core-testing branch. - Convert imports touched by this series to vertical style. v4: - Refactor the SIZE constant to be an associated constant. (Alice) - Remove the default method implementations in the Io trait. (Alice) - Make cfg_size() private. (Danilo/Bjorn) - Implement the infallible accessors of ConfigSpace. (Danilo) - Create a new Io64 trait specifically for 64-bit accessors. (Danilo) - Provide two separate methods for driver: config_space() and config_space_extended(). (Danilo) - Update the sample driver to test the infallible accessors. (Danilo) v3: - Turn offset_valid() into a private function of kernel::io:Io. (Alex) - Separate try and non-try variants. (Danilo) - Move all the {try_}{read,write}{8,16,32,64} accessors to the I/O trait. (Danilo) - Replace the hardcoded MMIO type constraint with a generic trait bound so that register! macro can be used in other places. (Danilo) - Fix doctest. (John) - Add an enum for PCI configuration space size. (Danilo) - Refine the patch comments. (Bjorn) v2: - Factor out common trait as 'Io' and keep the rest routines in original 'Io' as 'Mmio'. (Danilo) - Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implementation to use 'MmioRaw'. - Introduce pci::Device::config_space(). (Danilo) - Implement both infallible and fallible read/write routines, the device driver decicdes which version should be used. This ideas of this series are: - Factor out common traits for other accessors to share the same compiling/runtime check like before. - Introduce IoCapable and IoTryCapable traits to allow backends to selectively implement only the operations they support. - Factor the MMIO read/write macros from the define_read! and define_write! macros. Thus, define_{read, write}! can be used in other backends. In detail: * Introduce `call_mmio_read!` and `call_mmio_write!` helper macros to encapsulate the unsafe FFI calls. * Update `define_read!` and `define_write!` macros to delegate to the call macros. * Export `define_read` and `define_write` so they can be reused for other I/O backends (e.g. PCI config space). - Implement the PCI configuration space access backend in PCI abstractions. - Add tests for config space routines in rust PCI sample driver. [1] https://lore.kernel.org/all/20250903221111.3866249-1-zhiw@nvidia.com/ [2] https://lore.kernel.org/all/DEOMBKIRDXH6.2CF2MR2RB2W2C@nvidia.com/ [3] https://github.com/zhiwang-nvidia/nova-core/tree/rust-for-linux/pci-configuration-space-v11 Zhi Wang (5): rust: devres: style for imports rust: io: separate generic I/O helpers from MMIO implementation rust: io: factor out MMIO read/write macros rust: pci: add config space read/write support sample: rust: pci: add tests for config space routines drivers/gpu/drm/tyr/regs.rs | 1 + drivers/gpu/nova-core/gsp/sequencer.rs | 5 +- drivers/gpu/nova-core/regs/macros.rs | 90 +++-- drivers/gpu/nova-core/vbios.rs | 1 + drivers/pwm/pwm_th1520.rs | 5 +- rust/kernel/devres.rs | 35 +- rust/kernel/io.rs | 494 +++++++++++++++++++++---- rust/kernel/io/mem.rs | 16 +- rust/kernel/io/poll.rs | 16 +- rust/kernel/pci/io.rs | 171 ++++++++- samples/rust/rust_driver_pci.rs | 32 ++ 11 files changed, 722 insertions(+), 144 deletions(-) -- 2.51.0