From: Alex Williamson <alex@shazbot.org>
To: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Lukas Wunner <lukas@wunner.de>, <smadhavan@nvidia.com>,
<dave@stgolabs.net>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<bhelgaas@google.com>, <ming.li@zohomail.com>, <rrichter@amd.com>,
<Smita.KoralahalliChannabasappa@amd.com>,
<huaisheng.ye@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <vaslot@nvidia.com>,
<vsethi@nvidia.com>, <sdonthineni@nvidia.com>,
<vidyas@nvidia.com>, <mochs@nvidia.com>, <jsequeira@nvidia.com>,
"Terry Bowman" <terry.bowman@amd.com>
Subject: Re: [PATCH v4 09/10] PCI: save/restore CXL config around reset
Date: Mon, 26 Jan 2026 15:34:35 -0700 [thread overview]
Message-ID: <20260126153435.5f1557df@shazbot.org> (raw)
In-Reply-To: <20260122104745.00001fea@huawei.com>
On Thu, 22 Jan 2026 10:47:45 +0000
Jonathan Cameron <jonathan.cameron@huawei.com> wrote:
> On Thu, 22 Jan 2026 11:01:57 +0100
> Lukas Wunner <lukas@wunner.de> wrote:
>
> > On Tue, Jan 20, 2026 at 10:26:09PM +0000, smadhavan@nvidia.com wrote:
> > > +++ b/drivers/pci/pci.c
> > > @@ -4989,6 +4990,11 @@ static int cxl_reset(struct pci_dev *dev, bool probe)
> > > if (probe)
> > > return 0;
> > >
> > > + pci_save_state(dev);
> > > + rc = cxl_config_save_state(dev, &cxl_state);
> > > + if (rc)
> > > + pci_warn(dev, "Failed to save CXL config state: %d\n", rc);
> > > +
> >
> > Hm, shouldn't the call to cxl_config_save_state() be moved to
> > pci_save_state() (and likewise, cxl_config_restore_state() moved to
> > pci_restore_state())?
> >
> > E.g. when a DPC event occurs, I assume CXL registers need to
> > be restored as well on recovery, right?
> The CXL spec has some comic language around DPC that basically says
> "use with care, DPC trigger will bring down physical link, reset devicestate,
> disrupt CXL.cache and CXL.mem traffic".
> or in shorter words
> 'Good luck'
>
> If a CXL device undergoes DPC high chance you'll either trigger CXL isolation
> which we aren't handing yet in Linux because we aren't convinced software
> can really recover form it, or stall a CPU and end up rebooting.
>
> Maybe we'll one day we'll figure this out. Today turn off DPC on CXL ports! :)
Even if we hand-wave that DPC isn't an issue, save/restore of the PCI
state happens at a higher level for every other PCI reset method and
we're creating inconsistency here.
PCI-core includes interfaces for saving PCI state, offloading PCI state
as an opaque blob, reloading, and restoring that state, and performing
resets without saving and restoring state. This has a couple users,
including vfio.
If we want similar behavior for CXL type2 devices for a future vfio use
case, we shouldn't create unnecessary differentiation here with saving
the CXL state separately and making the reset method behave
differently. Thanks,
Alex
next prev parent reply other threads:[~2026-01-26 22:34 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-20 22:26 [PATCH v4 0/10] CXL Reset support for Type 2 devices smadhavan
2026-01-20 22:26 ` [PATCH v4 01/10] cxl: move DVSEC defines to cxl pci header smadhavan
2026-01-21 10:31 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 02/10] PCI: switch CXL port DVSEC defines smadhavan
2026-01-21 10:34 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 03/10] cxl: add type 2 helper and reset DVSEC bits smadhavan
2026-01-20 23:27 ` Dave Jiang
2026-01-21 10:45 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 04/10] PCI: add CXL reset method smadhavan
2026-01-21 0:08 ` Dave Jiang
2026-01-21 10:57 ` Jonathan Cameron
2026-01-23 13:54 ` kernel test robot
2026-01-20 22:26 ` [PATCH v4 05/10] cxl: add reset prepare and region teardown smadhavan
2026-01-21 11:09 ` Jonathan Cameron
2026-01-21 21:25 ` Dave Jiang
2026-01-20 22:26 ` [PATCH v4 06/10] PCI: wire CXL reset prepare/cleanup smadhavan
2026-01-21 22:13 ` Dave Jiang
2026-01-22 2:17 ` Srirangan Madhavan
2026-01-22 15:11 ` Dave Jiang
2026-01-24 7:54 ` kernel test robot
2026-01-20 22:26 ` [PATCH v4 07/10] cxl: add host cache flush and multi-function reset smadhavan
2026-01-21 11:20 ` Jonathan Cameron
2026-01-21 20:27 ` Davidlohr Bueso
2026-01-22 9:53 ` Jonathan Cameron
2026-01-21 22:19 ` Vikram Sethi
2026-01-22 9:40 ` Souvik Chakravarty
[not found] ` <PH7PR12MB9175CDFC163843BB497073CEBD96A@PH7PR12MB9175.namprd12.prod.outlook.com>
2026-01-22 10:31 ` Jonathan Cameron
2026-01-22 19:24 ` Vikram Sethi
2026-01-23 13:13 ` Jonathan Cameron
2026-01-21 23:59 ` Dave Jiang
2026-01-20 22:26 ` [PATCH v4 08/10] cxl: add DVSEC config save/restore smadhavan
2026-01-21 11:31 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 09/10] PCI: save/restore CXL config around reset smadhavan
2026-01-21 22:32 ` Dave Jiang
2026-01-22 10:01 ` Lukas Wunner
2026-01-22 10:47 ` Jonathan Cameron
2026-01-26 22:34 ` Alex Williamson [this message]
2026-03-12 18:24 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 10/10] cxl: add HDM decoder and IDE save/restore smadhavan
2026-01-21 11:42 ` Jonathan Cameron
2026-01-22 15:09 ` Dave Jiang
2026-01-21 1:19 ` [PATCH v4 0/10] CXL Reset support for Type 2 devices Alison Schofield
2026-01-22 0:00 ` Bjorn Helgaas
2026-01-27 16:33 ` Alex Williamson
2026-01-27 17:02 ` dan.j.williams
2026-01-27 18:07 ` Vikram Sethi
2026-01-28 3:42 ` dan.j.williams
2026-01-28 12:36 ` Jonathan Cameron
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