[PATCH 0/2] PCI: dwc: Expose integrated DesignWare eDMA windows

[PATCH 0/2] PCI: dwc: Expose integrated DesignWare eDMA windows

[Koichiro Den]

This series adds small, query-only helper APIs to the DesignWare PCIe
endpoint controller driver to expose resources of an integrated
DesignWare eDMA instance. Specifically, it allows querying:

  - the physical base address and size of the integrated eDMA register
    aperture, and
  - the per-channel linked-list (LL) region base and size, keyed by
    transfer direction and hardware channel identifier.

The motivation is that some DesignWare PCIe endpoint platforms integrate
an eDMA engine that can be driven either locally by the endpoint or
remotely by the host. Remote eDMA use cases (e.g. [1]) need to expose
the eDMA register block and LL regions to the host through PCIe BARs,
while still allowing the endpoint to boot with a standard EP settings,
without DT changes to hide the eDMA instance from the endpoint itself.

The hardware channel identifier used by the LL-region helper can be
obtained via dma_get_slave_caps().hw_id, introduced by a dmaengine
series posted separately.

[1] [RFC PATCH v4 00/38] NTB transport backed by PCI EP embedded DMA
    https://lore.kernel.org/linux-pci/20260118135440.1958279-1-den@valinux.co.jp/

Developed on PCI controller/dwc:
  commit 0ecd890e3cf5 ("PCI: dwc: Rename dw_pcie_rp::has_msi_ctrl to
                        dw_pcie_rp::use_imsi_rx for clarity")

Kind regards,

Koichiro Den (2):
  PCI: dwc: Add helper to query integrated dw-edma register window
  PCI: dwc: Add helper to query integrated dw-edma linked-list region

 MAINTAINERS                                  |  2 +-
 drivers/pci/controller/dwc/pcie-designware.c | 74 ++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h |  2 +
 include/linux/pcie-dwc-edma.h                | 72 +++++++++++++++++++
 4 files changed, 149 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/pcie-dwc-edma.h

-- 
2.51.0

[PATCH 1/2] PCI: dwc: Add helper to query integrated dw-edma register window

[Koichiro Den]

Some DesignWare PCIe endpoint controllers integrate a DesignWare eDMA
instance. Remote-eDMA providers (e.g. vNTB) need to expose the eDMA
register block to the host through a memory window so the host can
ioremap it and run dw_edma_probe() against the remote view.

Record the physical base and size of the eDMA register aperture and
export dwc_pcie_edma_get_reg_window() so higher-level code can query the
register window associated with a given PCI EPC device.

Keep the controller-side helper declarations in a dedicated header to
avoid pulling eDMA/dmaengine-specific interfaces into the generic
DesignWare PCIe header (include/linux/pcie-dwc.h).

Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
 MAINTAINERS                                  |  2 +-
 drivers/pci/controller/dwc/pcie-designware.c | 29 +++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h |  2 +
 include/linux/pcie-dwc-edma.h                | 39 ++++++++++++++++++++
 4 files changed, 71 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/pcie-dwc-edma.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 5b11839cba9d..fa0cb454744c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20066,7 +20066,7 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
 F:	Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
 F:	drivers/pci/controller/dwc/*designware*
-F:	include/linux/pcie-dwc.h
+F:	include/linux/pcie-dwc*.h
 
 PCI DRIVER FOR TI DRA7XX/J721E
 M:	Vignesh Raghavendra <vigneshr@ti.com>
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 18331d9e85be..bbaeecce199a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -18,6 +18,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/pcie-dwc.h>
+#include <linux/pcie-dwc-edma.h>
 #include <linux/platform_device.h>
 #include <linux/sizes.h>
 #include <linux/types.h>
@@ -162,8 +163,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
 			pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
 			if (IS_ERR(pci->edma.reg_base))
 				return PTR_ERR(pci->edma.reg_base);
+			pci->edma_reg_phys = res->start;
+			pci->edma_reg_size = resource_size(res);
 		} else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
 			pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
+			pci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;
+			pci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;
 		}
 	}
 
@@ -1340,3 +1345,27 @@ resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
 
 	return cpu_phys_addr - reg_addr;
 }
+
+int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
+				 resource_size_t *sz)
+{
+	struct dw_pcie_ep *ep;
+	struct dw_pcie *pci;
+
+	if (!epc || !phys || !sz)
+		return -EINVAL;
+
+	ep = epc_get_drvdata(epc);
+	if (!ep)
+		return -ENODEV;
+
+	pci = to_dw_pcie_from_ep(ep);
+	if (!pci->edma_reg_size)
+		return -ENODEV;
+
+	*phys = pci->edma_reg_phys;
+	*sz = pci->edma_reg_size;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(dwc_pcie_edma_get_reg_window);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index c3301b3aedb7..cd38147443bf 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -534,6 +534,8 @@ struct dw_pcie {
 	int			max_link_speed;
 	u8			n_fts[2];
 	struct dw_edma_chip	edma;
+	phys_addr_t		edma_reg_phys;
+	resource_size_t		edma_reg_size;
 	bool			l1ss_support;	/* L1 PM Substates support */
 	struct clk_bulk_data	app_clks[DW_PCIE_NUM_APP_CLKS];
 	struct clk_bulk_data	core_clks[DW_PCIE_NUM_CORE_CLKS];
diff --git a/include/linux/pcie-dwc-edma.h b/include/linux/pcie-dwc-edma.h
new file mode 100644
index 000000000000..a5b0595603f4
--- /dev/null
+++ b/include/linux/pcie-dwc-edma.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * DesignWare PCIe controller helpers for integrated DesignWare eDMA.
+ */
+
+#ifndef LINUX_PCIE_DWC_EDMA_H
+#define LINUX_PCIE_DWC_EDMA_H
+
+#include <linux/errno.h>
+#include <linux/kconfig.h>
+#include <linux/pci-epc.h>
+#include <linux/types.h>
+
+#ifdef CONFIG_PCIE_DW
+/**
+ * dwc_pcie_edma_get_reg_window() - get integrated DW eDMA register window
+ * @epc:  EPC device associated with the integrated eDMA instance
+ * @phys: pointer to receive the CPU-physical base address
+ * @sz:   pointer to receive the size in bytes
+ *
+ * Some DesignWare PCIe endpoint controllers integrate a DesignWare eDMA
+ * instance. Higher-level code (e.g. BAR/window setup for remote use) may
+ * need the CPU-physical base and size of the eDMA register aperture.
+ *
+ * Return: 0 on success, -ENODEV if the EPC has no integrated eDMA register
+ *         window, or -EINVAL if @epc is %NULL.
+ */
+int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
+				 resource_size_t *sz);
+#else
+static inline int
+dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
+			     resource_size_t *sz)
+{
+	return -ENODEV;
+}
+#endif /* CONFIG_PCIE_DW */
+
+#endif /* LINUX_PCIE_DWC_EDMA_H */
-- 
2.51.0

Re: [PATCH 1/2] PCI: dwc: Add helper to query integrated dw-edma register window

[kernel test robot]

Hi Koichiro,

kernel test robot noticed the following build errors:

[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v6.19-rc7 next-20260126]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Koichiro-Den/PCI-dwc-Add-helper-to-query-integrated-dw-edma-register-window/20260126-152209
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20260126071550.3233631-2-den%40valinux.co.jp
patch subject: [PATCH 1/2] PCI: dwc: Add helper to query integrated dw-edma register window
config: um-randconfig-r071-20260127 (https://download.01.org/0day-ci/archive/20260127/202601271506.INKGUWyt-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
smatch version: v0.5.0-8994-gd50c5a4c
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260127/202601271506.INKGUWyt-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601271506.INKGUWyt-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/pci/controller/dwc/pcie-designware.c: In function 'dwc_pcie_edma_get_reg_window':
>> drivers/pci/controller/dwc/pcie-designware.c:1358:14: error: implicit declaration of function 'epc_get_drvdata'; did you mean 'epf_get_drvdata'? [-Wimplicit-function-declaration]
    1358 |         ep = epc_get_drvdata(epc);
         |              ^~~~~~~~~~~~~~~
         |              epf_get_drvdata
>> drivers/pci/controller/dwc/pcie-designware.c:1358:12: error: assignment to 'struct dw_pcie_ep *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
    1358 |         ep = epc_get_drvdata(epc);
         |            ^


vim +1358 drivers/pci/controller/dwc/pcie-designware.c

  1348	
  1349	int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
  1350					 resource_size_t *sz)
  1351	{
  1352		struct dw_pcie_ep *ep;
  1353		struct dw_pcie *pci;
  1354	
  1355		if (!epc || !phys || !sz)
  1356			return -EINVAL;
  1357	
> 1358		ep = epc_get_drvdata(epc);

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 1/2] PCI: dwc: Add helper to query integrated dw-edma register window

[kernel test robot]

Hi Koichiro,

kernel test robot noticed the following build errors:

[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v6.19-rc7 next-20260126]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Koichiro-Den/PCI-dwc-Add-helper-to-query-integrated-dw-edma-register-window/20260126-152209
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20260126071550.3233631-2-den%40valinux.co.jp
patch subject: [PATCH 1/2] PCI: dwc: Add helper to query integrated dw-edma register window
config: riscv-defconfig (https://download.01.org/0day-ci/archive/20260127/202601271718.STDXKWdE-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260127/202601271718.STDXKWdE-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601271718.STDXKWdE-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-designware.c:1358:7: error: call to undeclared function 'epc_get_drvdata'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
    1358 |         ep = epc_get_drvdata(epc);
         |              ^
   drivers/pci/controller/dwc/pcie-designware.c:1358:7: note: did you mean 'epf_get_drvdata'?
   include/linux/pci-epf.h:229:21: note: 'epf_get_drvdata' declared here
     229 | static inline void *epf_get_drvdata(struct pci_epf *epf)
         |                     ^
>> drivers/pci/controller/dwc/pcie-designware.c:1358:5: error: incompatible integer to pointer conversion assigning to 'struct dw_pcie_ep *' from 'int' [-Wint-conversion]
    1358 |         ep = epc_get_drvdata(epc);
         |            ^ ~~~~~~~~~~~~~~~~~~~~
   2 errors generated.


vim +/epc_get_drvdata +1358 drivers/pci/controller/dwc/pcie-designware.c

  1348	
  1349	int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
  1350					 resource_size_t *sz)
  1351	{
  1352		struct dw_pcie_ep *ep;
  1353		struct dw_pcie *pci;
  1354	
  1355		if (!epc || !phys || !sz)
  1356			return -EINVAL;
  1357	
> 1358		ep = epc_get_drvdata(epc);

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 1/2] PCI: dwc: Add helper to query integrated dw-edma register window

[kernel test robot]

Hi Koichiro,

kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.19-rc7 next-20260126]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Koichiro-Den/PCI-dwc-Add-helper-to-query-integrated-dw-edma-register-window/20260126-152209
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20260126071550.3233631-2-den%40valinux.co.jp
patch subject: [PATCH 1/2] PCI: dwc: Add helper to query integrated dw-edma register window
config: parisc-randconfig-001-20260127 (https://download.01.org/0day-ci/archive/20260127/202601271859.mmq8t4xv-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260127/202601271859.mmq8t4xv-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601271859.mmq8t4xv-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/pci/controller/dwc/pcie-designware.c: In function 'dwc_pcie_edma_get_reg_window':
   drivers/pci/controller/dwc/pcie-designware.c:1358:14: error: implicit declaration of function 'epc_get_drvdata'; did you mean 'epf_get_drvdata'? [-Werror=implicit-function-declaration]
    1358 |         ep = epc_get_drvdata(epc);
         |              ^~~~~~~~~~~~~~~
         |              epf_get_drvdata
>> drivers/pci/controller/dwc/pcie-designware.c:1358:12: warning: assignment to 'struct dw_pcie_ep *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
    1358 |         ep = epc_get_drvdata(epc);
         |            ^
   cc1: some warnings being treated as errors


vim +1358 drivers/pci/controller/dwc/pcie-designware.c

  1348	
  1349	int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
  1350					 resource_size_t *sz)
  1351	{
  1352		struct dw_pcie_ep *ep;
  1353		struct dw_pcie *pci;
  1354	
  1355		if (!epc || !phys || !sz)
  1356			return -EINVAL;
  1357	
> 1358		ep = epc_get_drvdata(epc);

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 2/2] PCI: dwc: Add helper to query integrated dw-edma linked-list region

[Koichiro Den]

Some DesignWare PCIe endpoint controllers integrate a DesignWare eDMA
instance and allocate per-channel linked-list (LL) regions. Remote eDMA
providers may need to expose those LL regions to the host so it can
build descriptors against the remote view.

Export dwc_pcie_edma_get_ll_region() to allow higher-level code to query
the LL region (base/size) for a given EPC, transfer direction
(DMA_DEV_TO_MEM / DMA_MEM_TO_DEV) and hardware channel identifier. The
helper maps the request to the appropriate read/write LL region
depending on whether the integrated eDMA is the local or the remote
view.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
 drivers/pci/controller/dwc/pcie-designware.c | 45 ++++++++++++++++++++
 include/linux/pcie-dwc-edma.h                | 33 ++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index bbaeecce199a..e8617873e832 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -1369,3 +1369,48 @@ int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
 	return 0;
 }
 EXPORT_SYMBOL_GPL(dwc_pcie_edma_get_reg_window);
+
+int dwc_pcie_edma_get_ll_region(struct pci_epc *epc,
+				enum dma_transfer_direction dir, int hw_id,
+				struct dw_edma_region *region)
+{
+	struct dw_edma_chip *chip;
+	struct dw_pcie_ep *ep;
+	struct dw_pcie *pci;
+	bool dir_read;
+
+	if (!epc || !region)
+		return -EINVAL;
+	if (dir != DMA_DEV_TO_MEM && dir != DMA_MEM_TO_DEV)
+		return -EINVAL;
+	if (hw_id < 0)
+		return -EINVAL;
+
+	ep = epc_get_drvdata(epc);
+	if (!ep)
+		return -ENODEV;
+
+	pci = to_dw_pcie_from_ep(ep);
+	chip = &pci->edma;
+
+	if (!chip->dev)
+		return -ENODEV;
+
+	if (chip->flags & DW_EDMA_CHIP_LOCAL)
+		dir_read = (dir == DMA_DEV_TO_MEM);
+	else
+		dir_read = (dir == DMA_MEM_TO_DEV);
+
+	if (dir_read) {
+		if (hw_id >= chip->ll_rd_cnt)
+			return -EINVAL;
+		*region = chip->ll_region_rd[hw_id];
+	} else {
+		if (hw_id >= chip->ll_wr_cnt)
+			return -EINVAL;
+		*region = chip->ll_region_wr[hw_id];
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(dwc_pcie_edma_get_ll_region);
diff --git a/include/linux/pcie-dwc-edma.h b/include/linux/pcie-dwc-edma.h
index a5b0595603f4..36afb4df1998 100644
--- a/include/linux/pcie-dwc-edma.h
+++ b/include/linux/pcie-dwc-edma.h
@@ -6,6 +6,8 @@
 #ifndef LINUX_PCIE_DWC_EDMA_H
 #define LINUX_PCIE_DWC_EDMA_H
 
+#include <linux/dma/edma.h>
+#include <linux/dmaengine.h>
 #include <linux/errno.h>
 #include <linux/kconfig.h>
 #include <linux/pci-epc.h>
@@ -27,6 +29,29 @@
  */
 int dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
 				 resource_size_t *sz);
+
+/**
+ * dwc_pcie_edma_get_ll_region() - get linked-list (LL) region for a HW channel
+ * @epc:    EPC device associated with the integrated eDMA instance
+ * @dir:    DMA transfer direction (%DMA_DEV_TO_MEM or %DMA_MEM_TO_DEV)
+ * @hw_id:  hardware channel identifier (equals to dw_edma_chan.id)
+ * @region: pointer to a region descriptor to fill in
+ *
+ * Some integrated DesignWare eDMA instances allocate per-channel linked-list
+ * (LL) regions for descriptor storage. This helper returns the LL region
+ * corresponding to @dir and @hw_id.
+ *
+ * The mapping between @dir and the underlying eDMA read/write LL region
+ * depends on whether the integrated eDMA instance represents a local or a
+ * remote view.
+ *
+ * Return: 0 on success, -EINVAL on invalid arguments (including out-of-range
+ *         @hw_id), or -ENODEV if the integrated eDMA instance is not present
+ *         or not initialized.
+ */
+int dwc_pcie_edma_get_ll_region(struct pci_epc *epc,
+				enum dma_transfer_direction dir, int hw_id,
+				struct dw_edma_region *region);
 #else
 static inline int
 dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
@@ -34,6 +59,14 @@ dwc_pcie_edma_get_reg_window(struct pci_epc *epc, phys_addr_t *phys,
 {
 	return -ENODEV;
 }
+
+static inline int
+dwc_pcie_edma_get_ll_region(struct pci_epc *epc,
+			    enum dma_transfer_direction dir, int hw_id,
+			    struct dw_edma_region *region)
+{
+	return -ENODEV;
+}
 #endif /* CONFIG_PCIE_DW */
 
 #endif /* LINUX_PCIE_DWC_EDMA_H */
-- 
2.51.0

Re: [PATCH 0/2] PCI: dwc: Expose integrated DesignWare eDMA windows

[Koichiro Den]

On Mon, Jan 26, 2026 at 04:15:48PM +0900, Koichiro Den wrote:
> This series adds small, query-only helper APIs to the DesignWare PCIe
> endpoint controller driver to expose resources of an integrated
> DesignWare eDMA instance. Specifically, it allows querying:
> 
>   - the physical base address and size of the integrated eDMA register
>     aperture, and
>   - the per-channel linked-list (LL) region base and size, keyed by
>     transfer direction and hardware channel identifier.
> 
> The motivation is that some DesignWare PCIe endpoint platforms integrate
> an eDMA engine that can be driven either locally by the endpoint or
> remotely by the host. Remote eDMA use cases (e.g. [1]) need to expose
> the eDMA register block and LL regions to the host through PCIe BARs,
> while still allowing the endpoint to boot with a standard EP settings,
> without DT changes to hide the eDMA instance from the endpoint itself.
> 
> The hardware channel identifier used by the LL-region helper can be
> obtained via dma_get_slave_caps().hw_id, introduced by a dmaengine
> series posted separately.

For reference, the series has been submitted here:

  [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
  https://lore.kernel.org/dmaengine/20260126073652.3293564-1-den@valinux.co.jp/

Kind regards,
Koichiro

> 
> [1] [RFC PATCH v4 00/38] NTB transport backed by PCI EP embedded DMA
>     https://lore.kernel.org/linux-pci/20260118135440.1958279-1-den@valinux.co.jp/
> 
> Developed on PCI controller/dwc:
>   commit 0ecd890e3cf5 ("PCI: dwc: Rename dw_pcie_rp::has_msi_ctrl to
>                         dw_pcie_rp::use_imsi_rx for clarity")
> 
> Kind regards,
> 
> Koichiro Den (2):
>   PCI: dwc: Add helper to query integrated dw-edma register window
>   PCI: dwc: Add helper to query integrated dw-edma linked-list region
> 
>  MAINTAINERS                                  |  2 +-
>  drivers/pci/controller/dwc/pcie-designware.c | 74 ++++++++++++++++++++
>  drivers/pci/controller/dwc/pcie-designware.h |  2 +
>  include/linux/pcie-dwc-edma.h                | 72 +++++++++++++++++++
>  4 files changed, 149 insertions(+), 1 deletion(-)
>  create mode 100644 include/linux/pcie-dwc-edma.h
> 
> -- 
> 2.51.0
> 

Re: [PATCH 0/2] PCI: dwc: Expose integrated DesignWare eDMA windows

[Frank Li]

On Mon, Jan 26, 2026 at 04:55:58PM +0900, Koichiro Den wrote:
> On Mon, Jan 26, 2026 at 04:15:48PM +0900, Koichiro Den wrote:
> > This series adds small, query-only helper APIs to the DesignWare PCIe
> > endpoint controller driver to expose resources of an integrated
> > DesignWare eDMA instance. Specifically, it allows querying:
> >
> >   - the physical base address and size of the integrated eDMA register
> >     aperture, and
> >   - the per-channel linked-list (LL) region base and size, keyed by
> >     transfer direction and hardware channel identifier.
> >
> > The motivation is that some DesignWare PCIe endpoint platforms integrate
> > an eDMA engine that can be driven either locally by the endpoint or
> > remotely by the host. Remote eDMA use cases (e.g. [1]) need to expose
> > the eDMA register block and LL regions to the host through PCIe BARs,
> > while still allowing the endpoint to boot with a standard EP settings,
> > without DT changes to hide the eDMA instance from the endpoint itself.
> >
> > The hardware channel identifier used by the LL-region helper can be
> > obtained via dma_get_slave_caps().hw_id, introduced by a dmaengine
> > series posted separately.
>
> For reference, the series has been submitted here:
>
>   [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
>   https://lore.kernel.org/dmaengine/20260126073652.3293564-1-den@valinux.co.jp/

It'd better post together. It needs API user.

Frank
>
> Kind regards,
> Koichiro
>
> >
> > [1] [RFC PATCH v4 00/38] NTB transport backed by PCI EP embedded DMA
> >     https://lore.kernel.org/linux-pci/20260118135440.1958279-1-den@valinux.co.jp/
> >
> > Developed on PCI controller/dwc:
> >   commit 0ecd890e3cf5 ("PCI: dwc: Rename dw_pcie_rp::has_msi_ctrl to
> >                         dw_pcie_rp::use_imsi_rx for clarity")
> >
> > Kind regards,
> >
> > Koichiro Den (2):
> >   PCI: dwc: Add helper to query integrated dw-edma register window
> >   PCI: dwc: Add helper to query integrated dw-edma linked-list region
> >
> >  MAINTAINERS                                  |  2 +-
> >  drivers/pci/controller/dwc/pcie-designware.c | 74 ++++++++++++++++++++
> >  drivers/pci/controller/dwc/pcie-designware.h |  2 +
> >  include/linux/pcie-dwc-edma.h                | 72 +++++++++++++++++++
> >  4 files changed, 149 insertions(+), 1 deletion(-)
> >  create mode 100644 include/linux/pcie-dwc-edma.h
> >
> > --
> > 2.51.0
> >

Re: [PATCH 0/2] PCI: dwc: Expose integrated DesignWare eDMA windows

[Koichiro Den]

On Mon, Jan 26, 2026 at 12:47:51PM -0500, Frank Li wrote:
> On Mon, Jan 26, 2026 at 04:55:58PM +0900, Koichiro Den wrote:
> > On Mon, Jan 26, 2026 at 04:15:48PM +0900, Koichiro Den wrote:
> > > This series adds small, query-only helper APIs to the DesignWare PCIe
> > > endpoint controller driver to expose resources of an integrated
> > > DesignWare eDMA instance. Specifically, it allows querying:
> > >
> > >   - the physical base address and size of the integrated eDMA register
> > >     aperture, and
> > >   - the per-channel linked-list (LL) region base and size, keyed by
> > >     transfer direction and hardware channel identifier.
> > >
> > > The motivation is that some DesignWare PCIe endpoint platforms integrate
> > > an eDMA engine that can be driven either locally by the endpoint or
> > > remotely by the host. Remote eDMA use cases (e.g. [1]) need to expose
> > > the eDMA register block and LL regions to the host through PCIe BARs,
> > > while still allowing the endpoint to boot with a standard EP settings,
> > > without DT changes to hide the eDMA instance from the endpoint itself.
> > >
> > > The hardware channel identifier used by the LL-region helper can be
> > > obtained via dma_get_slave_caps().hw_id, introduced by a dmaengine
> > > series posted separately.
> >
> > For reference, the series has been submitted here:
> >
> >   [PATCH 0/5] dmaengine: dw-edma: Add helpers for remote eDMA use scenarios
> >   https://lore.kernel.org/dmaengine/20260126073652.3293564-1-den@valinux.co.jp/
> 
> It'd better post together. It needs API user.

Thanks for the comment. I've sent v2, please see:
https://lore.kernel.org/all/20260127033420.3460579-1-den@valinux.co.jp/

Koichiro

> 
> Frank
> >
> > Kind regards,
> > Koichiro
> >
> > >
> > > [1] [RFC PATCH v4 00/38] NTB transport backed by PCI EP embedded DMA
> > >     https://lore.kernel.org/linux-pci/20260118135440.1958279-1-den@valinux.co.jp/
> > >
> > > Developed on PCI controller/dwc:
> > >   commit 0ecd890e3cf5 ("PCI: dwc: Rename dw_pcie_rp::has_msi_ctrl to
> > >                         dw_pcie_rp::use_imsi_rx for clarity")
> > >
> > > Kind regards,
> > >
> > > Koichiro Den (2):
> > >   PCI: dwc: Add helper to query integrated dw-edma register window
> > >   PCI: dwc: Add helper to query integrated dw-edma linked-list region
> > >
> > >  MAINTAINERS                                  |  2 +-
> > >  drivers/pci/controller/dwc/pcie-designware.c | 74 ++++++++++++++++++++
> > >  drivers/pci/controller/dwc/pcie-designware.h |  2 +
> > >  include/linux/pcie-dwc-edma.h                | 72 +++++++++++++++++++
> > >  4 files changed, 149 insertions(+), 1 deletion(-)
> > >  create mode 100644 include/linux/pcie-dwc-edma.h
> > >
> > > --
> > > 2.51.0
> > >