[PATCH] PCI: dwc: ep: Fix regression in dw_pcie_ep_raise_msi_irq()

[Niklas Cassel <cassel@kernel.org>]

When using the nvmet-pci-epf EPF driver, and starting the EP before
starting a host with UEFI, the UEFI performs NVMe commands e.g.
Identify Controller, to get the name of the controller.

nvmet-pci-epf will post the CQE (completion queue entry) to the Admin
Completion Queue, and then raise an IRQ (using
dw_pcie_ep_raise_msi_irq()).

Once the host boots Linux, we will see a WARN_ON_ONCE() from
dw_pcie_ep_raise_msi_irq(), and then the booting of the host hangs,
because it never gets an IRQ when loading the nvme driver.

The reason is that the MSI target address used by UEFI and Linux might
be different, which will cause dw_pcie_ep_raise_msi_irq() to simply
return -EINVAL.

This was working before commit 8719c64e76bf ("PCI: dwc: ep: Cache MSI
outbound iATU mapping"), so this is a regression.

Also, remove the warning, as we cannot know if there are operations in
flight or not, so it seems wrong to print this warning unconditionally
at every boot when e.g. nvmet-pci-epf is used with a host with UEFI.

Fixes: 8719c64e76bf ("PCI: dwc: ep: Cache MSI outbound iATU mapping")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 .../pci/controller/dwc/pcie-designware-ep.c   | 22 +++++++++++--------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7e7844ff0f7e..5d8024d5e5c6 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -896,6 +896,19 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 	 * supported, so we avoid reprogramming the region on every MSI,
 	 * specifically unmapping immediately after writel().
 	 */
+	if (ep->msi_iatu_mapped && (ep->msi_msg_addr != msg_addr ||
+				    ep->msi_map_size != map_size)) {
+		/*
+		 * The host changed the MSI target address or the required
+		 * mapping size changed. Reprogramming the iATU when there are
+		 * operations in flight is unsafe on this controller. However,
+		 * there is no unified way to check if we have operations in
+		 * flight, thus we don't know if we should WARN() or not.
+		 */
+		dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
+		ep->msi_iatu_mapped = false;
+	}
+
 	if (!ep->msi_iatu_mapped) {
 		ret = dw_pcie_ep_map_addr(epc, func_no, 0,
 					  ep->msi_mem_phys, msg_addr,
@@ -906,15 +919,6 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 		ep->msi_iatu_mapped = true;
 		ep->msi_msg_addr = msg_addr;
 		ep->msi_map_size = map_size;
-	} else if (WARN_ON_ONCE(ep->msi_msg_addr != msg_addr ||
-				ep->msi_map_size != map_size)) {
-		/*
-		 * The host changed the MSI target address or the required
-		 * mapping size changed. Reprogramming the iATU at runtime is
-		 * unsafe on this controller, so bail out instead of trying to
-		 * update the existing region.
-		 */
-		return -EINVAL;
 	}
 
 	writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);

base-commit: 43d324eeb08c3dd9fff7eb9a2c617afd3b96e65c
-- 
2.53.0