Re: [PATCH] PCI: dwc: ep: Fix regression in dw_pcie_ep_raise_msi_irq()

[Bjorn Helgaas <helgaas@kernel.org>]

On Wed, Feb 11, 2026 at 09:52:34AM +0100, Niklas Cassel wrote:
> On Tue, Feb 10, 2026 at 02:39:49PM -0600, Bjorn Helgaas wrote:
> > On Tue, Feb 10, 2026 at 09:22:58PM +0100, Niklas Cassel wrote:
> > > On Tue, Feb 10, 2026 at 01:32:05PM -0600, Bjorn Helgaas wrote:
> > 
> > The scenario I'm asking about is the following, where the single
> > change of MSI target as the host boots is concurrent with
> > dw_pcie_ep_raise_msi_irq()::
> > 
> >   - host writes PCI_MSI_ADDRESS_LO
> > 
> >   - dw_pcie_ep_raise_msi_irq() reads PCI_MSI_ADDRESS_LO and
> >     PCI_MSI_ADDRESS_HI
> > 
> >   - dw_pcie_ep_raise_msi_irq() maps msg_addr built from an old
> >     PCI_MSI_ADDRESS_HI and a new PCI_MSI_ADDRESS_LO
> > 
> >   - host writes PCI_MSI_ADDRESS_HI
> > 
> > This could be mitigated by re-reading PCI_MSI_ADDRESS_* to detect the
> > tearing.
> 
> Ok, now I understand.
> 
> This must be extremely unlikely to happen.
> 
> Since the host writes the MSI target address very early, before even
> enumerating the bus.
> 
> So the EP reading a half updated 64-bit MSI address, seems very
> unlikely.

Very unlikely for sure, and the patch is OK with me as-is, although
writing to the wrong address would be very difficult to debug.

I think it's probably more important to pay attention to the MSI and
MSI-X enable bits to make sure we don't generate MSIs when disabled.