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X-Microsoft-Antispam-Message-Info: 2OnjpZWTbXI7G6QiitJ+oEHalpys1CVzgt92A+DbdEnsL/hBsGzz2UZDTZeFytI+Jo3qwRJ3TPvJeWAfEgGGoref8eqaFlVAIf7AbJWjoA82O2WVOZvWaoayFqZ6zBygYLWnyFG+rZHnz60RjnO6sqTVjBz4Nh6Oe+96jVzdPkg7ez6WHtZc3Xy5cz+0S+kwhKJHGl3k0LeUVcz+XnF97oB2j0RC3fRa/8P2ip9btqAJn+Rie7mmKmCVpxExp8Jkx8OFFoujdxy6YnekqS0U7Im+cFGdFJYd5cS2FzdNWA5I199Z2/Z1KO2+yHkglnezANtobiJNflphgaGCqJksWmk5DDLIHknX7fN74QsN1dBgl1OVB9W1U0h6xptBGto7qXddn5jif4kL9/EibhN6E2ojDAuZfyDe73GUpCsE4gSoIvdWFnHA+dtfjse6SUA5yUTPf6fF3C0ydKVD/4e0cq0EAijoUMV6v/bcAzpmwkP27Z30Kt7Cu6S2pkvAiXk/u4HeqRVD0bQTe4DsNXfI2wbr7wsQ8WttDHEfUyY4E6RCYnpDfJUX1/RwxNYX8/SNGTOJbCyqBo7+ai2gMt8bO5k36DmGuvEEiXyIFHtoDg/KwkMuVnw5MXVaR2maW7jHTGFnPB5W9F0RLBFs3c+q75+WpWNoXMrYvwqkISRe264pw3NBOf3yoZ/jt2dRP6KLCcgEkdyur6T1v9d/txfu2IGsAEFcYHyiw0Cdmq4+ajjslxevN580zJH+T53KTWTAxGACJYZoBH+/BJjwwXPEIEq+GsPUBFSQw5u1DOe4Eyua0cBpLA/eODZ5n1HiExW6sWNRhE6noAKHHN7L5+wgCw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dKupTwN1XRJcz20LR2h3dbHZqehqeOSJWE8Last2MDEPmEsce/VerjhZ3bo+KT2zwoJmbhY2kpnPfyMEUHClnYdjdXW++xImsU5i6LfaB+vfZW9vUh4d9FlKX3VR+62ES0su4kQFn5xI4lMQzTF2pEKoe8IE0d1YvHOdKKC4uVnL68hR2fM/FRb4JuziZcDm0dYcRUxVM7bXNHTSx/jCcdoYULVP1XuYYNpR8WX2QJtSQIF47JpJJT+BdE2UPkytZ8vKemJt26ML56Qz6AWlwwrk3q+9AlXUIT01sMUxoxAfMkawX4XhWCJdLhBQq4qofFz0tC2whOAxJDzB4gOLAuvTg0OPs3F+ZUGKD8Dn9VWBc6Ratyvm1aWUroiMYiBeI+6OngDC2ZN1TtIgm5Rw5DW6QUxj+hWLz2/SNeeCtOjLOvpExTj65q9TVC32F8uu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2026 13:38:35.8552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bd51464-a2bc-46a5-4b1e-08de74732d1e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6604 The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines the "Unmask SBR" bit in the Port Control Extensions Register. When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit in the Bridge Control register has no effect on the downstream bus. Currently, the Linux PCI core checks this condition in pci_reset_bus_function(). If SBR is masked, it returns -ENOTTY during the execution of the reset. However, during the probe phase (when probe=true), the function currently returns 0. This 0 return value incorrectly signals to the PCI subsystem that SBR is a viable reset method for the device. As a result, 'bus' is listed in the device's /sys/bus/pci/devices/.../reset_methods attribute, even though the hardware is incapable of performing it. If a user attempts to write bus to reset method or triggers a reset that falls back to SBR, the operation fails with: "bash: echo: write error: Inappropriate ioctl for device" error. This patch modifies pci_reset_bus_function() to return -ENOTTY immediately if cxl_sbr_masked() is true, regardless of the probe argument. This ensures that 'bus' is not advertised in reset_methods when the hardware prevents it, improving clarity for users and aligning the sysfs capability report with actual hardware behavior. Signed-off-by: Vidya Sagar --- v2: * Before deciding to hide 'bus' reset method, add an extra check to make sure that the link is indeed operating in the CXL mode and not in PCIe mode as the spec clearly says that a '0' in 'Unmask SBR' doesn't have any effect if the link is not operating in the CXL mode. drivers/pci/pci.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f3244630bfd0..a176566ba56f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4915,12 +4915,8 @@ static int pci_reset_bus_function(struct pci_dev *dev, bool probe) * If "dev" is below a CXL port that has SBR control masked, SBR * won't do anything, so return error. */ - if (bridge && cxl_sbr_masked(bridge)) { - if (probe) - return 0; - + if (bridge && bridge->is_cxl && cxl_sbr_masked(bridge)) return -ENOTTY; - } rc = pci_dev_reset_iommu_prepare(dev); if (rc) { -- 2.25.1