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Mon, 2 Mar 2026 23:20:48 -0800 From: Manikanta Maddireddy To: , , , , , , , , , , , , , , , , , , <18255117159@163.com> CC: , , , Manikanta Maddireddy Subject: [PATCH v2 4/5] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED Date: Tue, 3 Mar 2026 12:50:03 +0530 Message-ID: <20260303072004.2384079-5-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260303072004.2384079-1-mmaddireddy@nvidia.com> References: <20260303072004.2384079-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C618E:EE_|CYYPR12MB8752:EE_ X-MS-Office365-Filtering-Correlation-Id: cd865aba-9198-4d72-23c2-08de78f57597 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013|921020; X-Microsoft-Antispam-Message-Info: hU/FriUDJwKmjyXDXTmpJ5Bo3XCDlMTmxIkq2BgqLT/cT+BApUpKxxt62pSSAcxR/vwi0DnmF4zZShoLsWB3MYjayVgcPhuGIic2/a9JqxOLTV3S7uO+CcJO/5M01OSzrDRlDAXBipmEZwWUepsnnvGo3wqGvyFtg218TmJnTa23HDSs7CcWBcT+zOIGBL6CzmLhIb3EjEdDp1ATYkZqb8UaHnPQA77dN0iYs6D8bKNtIFvrP6v06bIRhk9OAPJWWQ5aMfrClIlBEkSqm+XztWsunDOqu6nE4c5sUDirSIYcfEuM/C6x86qf+GgWl3E/XIgxiK/wbbqEbpiLAs5imblSZWnTawFEROZBznZo1roELxvOUF9zFJft/plT/hUGOcNRNFIGkBA8fOB9VwMQ4DmDYLdvzCop3dLnGN5WbZ+YerZ8u/3ukHsw831rxVkb4K94DxmINJf43QK3ztPE9UuitL6H7UjDAMWUlrxcLxFZblvRG/ctS9orAumeszONMPR4VGAE/0L25KA9qzl0PZKlidcRWf/tlyPedjPrUl15zbVTFi7saz63bzngY9eN1CT6kdeeRlfHzFDLMB8B+7Ws4CfuDnLrNeQ28DuVNNG3e0hqgJyVYW0g3RQLSz1wwq3SplLmGLwcHroYud65HucSyBUux4MZPEXa5zYD+NsfQHkE1B9lQnLU5+IhpvHEa+F+rONCyT0gU+U3IgvCg0TSJD9jjjWy2HCICpp3cdpijWVlx3JuYAcbBBEBBvGG2dFm2KeGwPMvIWmiVrzE5KH9+UAhl8KlTOOCk/YHtAAVXYVCK5Ea+rpSTcrY37cFMa7VtcuA5gt6jOQBKQ5vwJTATR11kvwJuejC++dfjDs= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dZaHkeyHMd+Jo99arDABjeCToPxWNjCJn6fCgdB+sLVSjCfol9Og05v0b0/yuh0Rs5iavO64ipffUNWOfq3CaQK/T7m/jg8xKtMlmYNW7Mg6HzLdqrhVepLRFc87Qaz1AhDpLsGKC6AEDvNbjKlah57l+Ka+jTwPnKTm+qmHcPyq5VnDdR8f6knPNThTGIdHXSUBZST6aF9p11fPkIvvQ6yAYNE3j1u6pJp3EMvGZ1W7Rq0V2gZoxgXiEkrjYQfOy582USHBH9gyKbhCyyGxDTyBLZyx++ayEKYTVBjiM8zPE53mkUiqitiqJTYB+hp0jEPkIaI/fSubixG0MKSCWRQvFBYftLyyMd4eEeK/pRFrP9q+D5LxMKfEWrLEEHS4Y5QRlcF8Ks4SVlNgzmDwJtrWuJluuyF3bLJZ301KHJAlr0dWbegtwcbe16VKsv5J X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2026 07:21:16.6830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd865aba-9198-4d72-23c2-08de78f57597 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C618E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8752 Tegra Endpoint exposes three 64-bit BARs at indices 0, 2, and 4: - BAR0+BAR1: EPF test/data (programmable 64-bit BAR) - BAR2+BAR3: MSI-X table (hardware-backed) - BAR4+BAR5: DMA registers (hardware-backed) Update tegra_pcie_epc_features so that BAR2 is BAR_RESERVED with PCI_EPC_BAR_RSVD_MSIX_TBL_RAM (64 KB) & PCI_EPC_BAR_RSVD_MSIX_PBA_RAM (64 KB), BAR3 is BAR_64BIT_UPPER, BAR4 is BAR_RESERVED with PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO (4KB), and BAR5 is BAR_64BIT_UPPER. This keeps CONSECUTIVE_BAR_TEST working while allowing the host to use 64-bit BAR2 (MSI-X) and BAR4 (DMA). Signed-off-by: Manikanta Maddireddy --- v2: Split MSI-X table and PBA reserved region drivers/pci/controller/dwc/pcie-tegra194.c | 44 +++++++++++++++++++--- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 2f35f18ba766..be60f80ccf6b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2001,16 +2001,50 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } -/* Tegra EP: BAR0 = 64-bit programmable BAR */ +static const struct pci_epc_bar_rsvd_region tegra194_bar2_rsvd[] = { + { + /* MSI-X table structure */ + .type = PCI_EPC_BAR_RSVD_MSIX_TBL_RAM, + .offset = 0x0, + .size = SZ_64K, + }, + { + /* MSI-X PBA structure */ + .type = PCI_EPC_BAR_RSVD_MSIX_PBA_RAM, + .offset = 0x10000, + .size = SZ_64K, + }, +}; + +static const struct pci_epc_bar_rsvd_region tegra194_bar4_rsvd[] = { + { + /* DMA_CAP (BAR4: DMA Port Logic Structure) */ + .type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO, + .offset = 0x0, + .size = SZ_4K, + }, +}; + +/* Tegra EP: BAR0 = 64-bit programmable BAR, BAR2 = 64-bit MSI-X table, BAR4 = 64-bit DMA regs. */ static const struct pci_epc_features tegra_pcie_epc_features = { .linkup_notifier = true, .msi_capable = true, .bar[BAR_0] = { .only_64bit = true, }, .bar[BAR_1] = { .type = BAR_64BIT_UPPER, }, - .bar[BAR_2] = { .type = BAR_DISABLED, }, - .bar[BAR_3] = { .type = BAR_DISABLED, }, - .bar[BAR_4] = { .type = BAR_DISABLED, }, - .bar[BAR_5] = { .type = BAR_DISABLED, }, + .bar[BAR_2] = { + .type = BAR_RESERVED, + .only_64bit = true, + .nr_rsvd_regions = ARRAY_SIZE(tegra194_bar2_rsvd), + .rsvd_regions = tegra194_bar2_rsvd, + }, + .bar[BAR_3] = { .type = BAR_64BIT_UPPER, }, + .bar[BAR_4] = { + .type = BAR_RESERVED, + .only_64bit = true, + .nr_rsvd_regions = ARRAY_SIZE(tegra194_bar4_rsvd), + .rsvd_regions = tegra194_bar4_rsvd, + }, + .bar[BAR_5] = { .type = BAR_64BIT_UPPER, }, .align = SZ_64K, }; -- 2.34.1