From: <smadhavan@nvidia.com>
To: <bhelgaas@google.com>, <dan.j.williams@intel.com>,
<dave.jiang@intel.com>, <jonathan.cameron@huawei.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>, <dave@stgolabs.net>
Cc: <alwilliamson@nvidia.com>, <jeshuas@nvidia.com>,
<vsethi@nvidia.com>, <skancherla@nvidia.com>, <vaslot@nvidia.com>,
<sdonthineni@nvidia.com>, <mhonap@nvidia.com>,
<vidyas@nvidia.com>, <jan@nvidia.com>, <mochs@nvidia.com>,
<dschumacher@nvidia.com>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
"Srirangan Madhavan" <smadhavan@nvidia.com>
Subject: [PATCH v5 1/7] PCI: Add CXL DVSEC reset and capability register definitions
Date: Fri, 6 Mar 2026 09:23:16 +0000 [thread overview]
Message-ID: <20260306092322.148765-2-smadhavan@nvidia.com> (raw)
In-Reply-To: <20260306092322.148765-1-smadhavan@nvidia.com>
From: Srirangan Madhavan <smadhavan@nvidia.com>
Add CXL DVSEC register definitions needed for CXL device reset per
CXL r3.2 section 8.1.3.1:
- Capability bits: RST_CAPABLE, CACHE_CAPABLE, CACHE_WBI_CAPABLE,
RST_TIMEOUT, RST_MEM_CLR_CAPABLE
- Control2 register: DISABLE_CACHING, INIT_CACHE_WBI, INIT_CXL_RST,
RST_MEM_CLR_EN
- Status2 register: CACHE_INV, RST_DONE, RST_ERR
- Non-CXL Function Map DVSEC register offset
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
include/uapi/linux/pci_regs.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 6fdc20d7f5e6..a9dcca54b01c 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1349,12 +1349,25 @@
/* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */
#define PCI_DVSEC_CXL_DEVICE 0
#define PCI_DVSEC_CXL_CAP 0xA
+#define PCI_DVSEC_CXL_CACHE_CAPABLE _BITUL(0)
#define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2)
#define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4)
+#define PCI_DVSEC_CXL_CACHE_WBI_CAPABLE _BITUL(6)
+#define PCI_DVSEC_CXL_RST_CAPABLE _BITUL(7)
+#define PCI_DVSEC_CXL_RST_TIMEOUT __GENMASK(10, 8)
+#define PCI_DVSEC_CXL_RST_MEM_CLR_CAPABLE _BITUL(11)
#define PCI_DVSEC_CXL_CTRL 0xC
#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2)
#define PCI_DVSEC_CXL_CTRL_RWL 0x5FED
#define PCI_DVSEC_CXL_CTRL2 0x10
+#define PCI_DVSEC_CXL_DISABLE_CACHING _BITUL(0)
+#define PCI_DVSEC_CXL_INIT_CACHE_WBI _BITUL(1)
+#define PCI_DVSEC_CXL_INIT_CXL_RST _BITUL(2)
+#define PCI_DVSEC_CXL_RST_MEM_CLR_EN _BITUL(3)
+#define PCI_DVSEC_CXL_STATUS2 0x12
+#define PCI_DVSEC_CXL_CACHE_INV _BITUL(0)
+#define PCI_DVSEC_CXL_RST_DONE _BITUL(1)
+#define PCI_DVSEC_CXL_RST_ERR _BITUL(2)
#define PCI_DVSEC_CXL_LOCK 0x14
#define PCI_DVSEC_CXL_LOCK_CONFIG _BITUL(0)
#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
@@ -1372,6 +1385,7 @@
/* CXL r4.0, 8.1.4: Non-CXL Function Map DVSEC */
#define PCI_DVSEC_CXL_FUNCTION_MAP 2
+#define PCI_DVSEC_CXL_FUNCTION_MAP_REG 0x0C
/* CXL r4.0, 8.1.5: Extensions DVSEC for Ports */
#define PCI_DVSEC_CXL_PORT 3
--
2.43.0
next prev parent reply other threads:[~2026-03-06 9:24 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-06 9:23 [PATCH v5 0/7] CXL: Add cxl_reset sysfs attribute for PCI devices smadhavan
2026-03-06 9:23 ` smadhavan [this message]
2026-03-06 9:23 ` [PATCH v5 2/7] PCI: Export pci_dev_save_and_disable() and pci_dev_restore() smadhavan
2026-03-06 9:23 ` [PATCH v5 3/7] cxl: Add memory offlining and cache flush helpers smadhavan
2026-03-06 23:34 ` Alex Williamson
2026-03-09 23:01 ` Dave Jiang
2026-03-06 9:23 ` [PATCH v5 4/7] cxl: Add multi-function sibling coordination for CXL reset smadhavan
2026-03-06 23:34 ` Alex Williamson
2026-03-06 9:23 ` [PATCH v5 5/7] cxl: Add CXL DVSEC reset sequence and flow orchestration smadhavan
2026-03-06 23:33 ` Alex Williamson
2026-03-10 0:26 ` Dave Jiang
2026-03-06 9:23 ` [PATCH v5 6/7] cxl: Add cxl_reset sysfs interface for PCI devices smadhavan
2026-03-06 23:32 ` Alex Williamson
2026-03-12 13:01 ` Jonathan Cameron
2026-03-14 20:39 ` Krzysztof Wilczyński
2026-03-06 9:23 ` [PATCH v5 7/7] Documentation: ABI: Add CXL PCI cxl_reset sysfs attribute smadhavan
2026-03-06 23:32 ` Alex Williamson
2026-03-09 22:37 ` [PATCH v5 0/7] CXL: Add cxl_reset sysfs attribute for PCI devices Dave Jiang
2026-03-09 22:40 ` Dave Jiang
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