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[83.28.48.214]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97846174cfsm236954366b.22.2026.03.14.17.54.10 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Sat, 14 Mar 2026 17:54:10 -0700 (PDT) Date: Sun, 15 Mar 2026 01:54:06 +0100 From: Michal Pecio To: linux-pci@vger.kernel.org, Bjorn Helgaas Cc: Alan Stern Subject: USB controller broken by zero cacheline size in PCIe to PCI bridge Message-ID: <20260315015406.533684d1.michal.pecio@gmail.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Hi, I have here a PCIe card with PEX8112 PCIe to PCI bridge and uPD720101 PCI USB controller (OHCI+EHCI) behind the bridge. The card works in one machine and gets sluggish and barely functional in another one. Hoping for some PCI misconfiguration, I ran lspci -vv on both machines for comparison (diff pasted below). There are surprisingly many differences, so I started to tweak with setpci on live system until I got it to work after setting CACHE_LINE_SIZE=10 on the bridge. The original value was zero. I rebooted and confirmed that this alone is sufficient, and changing back to zero immediately breaks the controller again. I know nothing about PCI, so I wonder if this result makes sense and what may be causing the "bad" system to end up in such sorry state? Thanks, Michal --- bad +++ good -07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) - Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- +02:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + BridgeCtl: Parity+ SERR+ NoISA+ VGA- VGA16- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) PCI-Express to PCI/PCI-X Bridge, IntMsgNum 0 DevCap: MaxPayload 128 bytes, PhantFunc 0 - ExtTag- AttnBtn- AttnInd- PwrInd- RBE- SlotPowerLimit 0W TEE-IO- + ExtTag- AttnBtn- AttnInd- PwrInd- RBE- SlotPowerLimit 25W TEE-IO- DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- NonFatalErr+ FatalErr- UnsupReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- - LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk- + LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1 TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Power Budgeting -08:00.0 USB controller: NEC Corporation OHCI USB Controller (rev 43) (prog-if 10 [OHCI]) +03:00.0 USB controller: NEC Corporation OHCI USB Controller (rev 43) (prog-if 10 [OHCI]) Subsystem: NEC Corporation USB Controller Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR-