* [PATCH] PCI: Use standard wait times for PCIe link monitoring
@ 2026-03-20 22:40 Thierry Reding
2026-03-20 22:47 ` Thierry Reding
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Thierry Reding @ 2026-03-20 22:40 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Karthikeyan Mitran,
Hou Zhiqiang, Thomas Petazzoni, Pali Rohár, Michal Simek,
Kevin Xie, linux-pci
From: Thierry Reding <treding@nvidia.com>
Instead of defining the wait values for each driver, use common values
defined in the core pci.h header file. Note that most drivers don't use
the millisecond waits, but rather usleep_range(), so add these commonly
used values to the header so that all drivers can use them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../pci/controller/cadence/pcie-cadence-host-common.c | 4 ++--
drivers/pci/controller/cadence/pcie-cadence-lga-regs.h | 5 -----
drivers/pci/controller/mobiveil/pcie-mobiveil.c | 4 ++--
drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 -----
drivers/pci/controller/pci-aardvark.c | 7 ++-----
drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++-------
drivers/pci/controller/plda/pcie-starfive.c | 9 ++-------
drivers/pci/pci.h | 2 ++
8 files changed, 12 insertions(+), 33 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
index 2b0211870f02..308844a5ed55 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
@@ -53,12 +53,12 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,
int retries;
/* Check if the link is up or not */
- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
if (pcie_link_up(pcie)) {
dev_info(dev, "Link up\n");
return 0;
}
- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+ usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
}
return -ETIMEDOUT;
diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h
index 857b2140c5d2..15dc4fcaf45d 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h
+++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h
@@ -10,11 +10,6 @@
#include <linux/bitfield.h>
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
-
/* Local Management Registers */
#define CDNS_PCIE_LM_BASE 0x00100000
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
index 62ecbaeb0a60..cc102032c1e6 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
@@ -218,11 +218,11 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
int retries;
/* check if the link is up or not */
- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
if (mobiveil_pcie_link_up(pcie))
return 0;
- usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
+ usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
}
dev_err(&pcie->pdev->dev, "link never came up\n");
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 7246de6a7176..11010a99e27c 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -122,11 +122,6 @@
#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
#define MAX_PIO_WINDOWS 8
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_MIN 90000
-#define LINK_WAIT_MAX 100000
-
#define PAGED_ADDR_BNDRY 0xc00
#define OFFSET_TO_PAGE_ADDR(off) \
((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index e34bea1ff0ac..506323a6c72b 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -255,9 +255,6 @@ enum {
#define PIO_RETRY_CNT 750000 /* 1.5 s */
#define PIO_RETRY_DELAY 2 /* 2 us*/
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
#define RETRAIN_WAIT_MAX_RETRIES 10
#define RETRAIN_WAIT_USLEEP_US 2000
@@ -349,11 +346,11 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
int retries;
/* check if the link is up or not */
- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
if (advk_pcie_link_up(pcie))
return 0;
- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+ usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
}
return -ETIMEDOUT;
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 7db2c96c6cec..fc65e9fdddb3 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -140,11 +140,6 @@
#define PCIE_PHY_LINKUP_BIT BIT(0)
#define PHY_RDY_LINKUP_BIT BIT(1)
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
-
struct nwl_msi { /* MSI information */
DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
struct irq_domain *dev_domain;
@@ -203,10 +198,10 @@ static int nwl_wait_for_link(struct nwl_pcie *pcie)
int retries;
/* check if the link is up or not */
- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
if (nwl_phy_link_up(pcie))
return 0;
- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+ usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
}
dev_err(dev, "PHY link never came up\n");
diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
index 298036c3e7f9..542a751b6f4d 100644
--- a/drivers/pci/controller/plda/pcie-starfive.c
+++ b/drivers/pci/controller/plda/pcie-starfive.c
@@ -45,11 +45,6 @@
#define STG_SYSCON_LNKSTA_OFFSET 0x170
#define DATA_LINK_ACTIVE BIT(5)
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
-
struct starfive_jh7110_pcie {
struct plda_pcie_rp plda;
struct reset_control *resets;
@@ -217,12 +212,12 @@ static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie)
int retries;
/* Check if the link is up or not */
- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+ for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
if (starfive_pcie_link_up(&pcie->plda)) {
dev_info(pcie->plda.dev, "port link up\n");
return 0;
}
- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+ usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
}
return -ETIMEDOUT;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index e542d1bf2853..0ca1c159b458 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -63,6 +63,8 @@ struct pcie_tlp_log;
/* Parameters for the waiting for link up routine */
#define PCIE_LINK_WAIT_MAX_RETRIES 10
#define PCIE_LINK_WAIT_SLEEP_MS 90
+#define PCIE_LINK_WAIT_US_MIN 90000
+#define PCIE_LINK_WAIT_US_MAX 100000
/* Format of TLP; PCIe r7.0, sec 2.2.1 */
#define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */
--
2.52.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] PCI: Use standard wait times for PCIe link monitoring
2026-03-20 22:40 [PATCH] PCI: Use standard wait times for PCIe link monitoring Thierry Reding
@ 2026-03-20 22:47 ` Thierry Reding
2026-03-21 9:44 ` kernel test robot
2026-03-21 10:17 ` kernel test robot
2 siblings, 0 replies; 4+ messages in thread
From: Thierry Reding @ 2026-03-20 22:47 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Karthikeyan Mitran,
Hou Zhiqiang, Thomas Petazzoni, Pali Rohár, Michal Simek,
Kevin Xie, linux-pci
[-- Attachment #1: Type: text/plain, Size: 1305 bytes --]
On Fri, Mar 20, 2026 at 11:40:44PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Instead of defining the wait values for each driver, use common values
> defined in the core pci.h header file. Note that most drivers don't use
> the millisecond waits, but rather usleep_range(), so add these commonly
> used values to the header so that all drivers can use them.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../pci/controller/cadence/pcie-cadence-host-common.c | 4 ++--
> drivers/pci/controller/cadence/pcie-cadence-lga-regs.h | 5 -----
> drivers/pci/controller/mobiveil/pcie-mobiveil.c | 4 ++--
> drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 -----
> drivers/pci/controller/pci-aardvark.c | 7 ++-----
> drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++-------
> drivers/pci/controller/plda/pcie-starfive.c | 9 ++-------
> drivers/pci/pci.h | 2 ++
> 8 files changed, 12 insertions(+), 33 deletions(-)
Ugh... sent this out and then noticed I hadn't committed the change
which adds the pci.h include for the Cadence driver I made after build
testing this.
I'll send out v2. Sorry for the noise.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] PCI: Use standard wait times for PCIe link monitoring
2026-03-20 22:40 [PATCH] PCI: Use standard wait times for PCIe link monitoring Thierry Reding
2026-03-20 22:47 ` Thierry Reding
@ 2026-03-21 9:44 ` kernel test robot
2026-03-21 10:17 ` kernel test robot
2 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2026-03-21 9:44 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas
Cc: oe-kbuild-all, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Karthikeyan Mitran,
Hou Zhiqiang, Thomas Petazzoni, Pali Rohár, Michal Simek,
Kevin Xie, linux-pci
Hi Thierry,
kernel test robot noticed the following build errors:
[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v7.0-rc4 next-20260320]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Thierry-Reding/PCI-Use-standard-wait-times-for-PCIe-link-monitoring/20260321-100847
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20260320224044.2569907-1-thierry.reding%40kernel.org
patch subject: [PATCH] PCI: Use standard wait times for PCIe link monitoring
config: s390-randconfig-001-20260321 (https://download.01.org/0day-ci/archive/20260321/202603211715.0eQRORig-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260321/202603211715.0eQRORig-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603211715.0eQRORig-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pci/controller/cadence/pcie-cadence-host-common.c: In function 'cdns_pcie_host_wait_for_link':
>> drivers/pci/controller/cadence/pcie-cadence-host-common.c:56:37: error: 'PCIE_LINK_WAIT_MAX_RETRIES' undeclared (first use in this function)
56 | for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pci/controller/cadence/pcie-cadence-host-common.c:56:37: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/pci/controller/cadence/pcie-cadence-host-common.c:61:30: error: 'PCIE_LINK_WAIT_US_MIN' undeclared (first use in this function)
61 | usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
| ^~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/cadence/pcie-cadence-host-common.c:61:53: error: 'PCIE_LINK_WAIT_US_MAX' undeclared (first use in this function)
61 | usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
| ^~~~~~~~~~~~~~~~~~~~~
vim +/PCIE_LINK_WAIT_MAX_RETRIES +56 drivers/pci/controller/cadence/pcie-cadence-host-common.c
48
49 int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,
50 cdns_pcie_linkup_func pcie_link_up)
51 {
52 struct device *dev = pcie->dev;
53 int retries;
54
55 /* Check if the link is up or not */
> 56 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
57 if (pcie_link_up(pcie)) {
58 dev_info(dev, "Link up\n");
59 return 0;
60 }
> 61 usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
62 }
63
64 return -ETIMEDOUT;
65 }
66 EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link);
67
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] PCI: Use standard wait times for PCIe link monitoring
2026-03-20 22:40 [PATCH] PCI: Use standard wait times for PCIe link monitoring Thierry Reding
2026-03-20 22:47 ` Thierry Reding
2026-03-21 9:44 ` kernel test robot
@ 2026-03-21 10:17 ` kernel test robot
2 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2026-03-21 10:17 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas
Cc: oe-kbuild-all, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Karthikeyan Mitran,
Hou Zhiqiang, Thomas Petazzoni, Pali Rohár, Michal Simek,
Kevin Xie, linux-pci
Hi Thierry,
kernel test robot noticed the following build errors:
[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v7.0-rc4 next-20260320]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Thierry-Reding/PCI-Use-standard-wait-times-for-PCIe-link-monitoring/20260321-100847
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20260320224044.2569907-1-thierry.reding%40kernel.org
patch subject: [PATCH] PCI: Use standard wait times for PCIe link monitoring
config: s390-randconfig-r071-20260321 (https://download.01.org/0day-ci/archive/20260321/202603211832.idChNb3Y-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 4abb927bacf37f18f6359a41639a6d1b3bffffb5)
smatch: v0.5.0-9004-gb810ac53
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260321/202603211832.idChNb3Y-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603211832.idChNb3Y-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/pci/controller/cadence/pcie-cadence-host-common.c:56:30: error: use of undeclared identifier 'PCIE_LINK_WAIT_MAX_RETRIES'
56 | for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/cadence/pcie-cadence-host-common.c:61:16: error: use of undeclared identifier 'PCIE_LINK_WAIT_US_MIN'
61 | usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
| ^~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/cadence/pcie-cadence-host-common.c:61:39: error: use of undeclared identifier 'PCIE_LINK_WAIT_US_MAX'
61 | usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
| ^~~~~~~~~~~~~~~~~~~~~
3 errors generated.
vim +/PCIE_LINK_WAIT_MAX_RETRIES +56 drivers/pci/controller/cadence/pcie-cadence-host-common.c
48
49 int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,
50 cdns_pcie_linkup_func pcie_link_up)
51 {
52 struct device *dev = pcie->dev;
53 int retries;
54
55 /* Check if the link is up or not */
> 56 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
57 if (pcie_link_up(pcie)) {
58 dev_info(dev, "Link up\n");
59 return 0;
60 }
> 61 usleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);
62 }
63
64 return -ETIMEDOUT;
65 }
66 EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link);
67
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 4+ messages in thread
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2026-03-20 22:40 [PATCH] PCI: Use standard wait times for PCIe link monitoring Thierry Reding
2026-03-20 22:47 ` Thierry Reding
2026-03-21 9:44 ` kernel test robot
2026-03-21 10:17 ` kernel test robot
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