Re: [PATCH v2 09/19] PCI/TSM: Support creating encrypted MMIO descriptors via TDISP Report

[Jason Gunthorpe <jgg@nvidia.com>]

On Tue, Apr 07, 2026 at 08:08:51AM +1000, Alexey Kardashevskiy wrote:
> 
> 
> On 4/4/26 01:08, Jason Gunthorpe wrote:
> > On Fri, Apr 03, 2026 at 11:41:25PM +1100, Alexey Kardashevskiy wrote:
> > > 
> > > 
> > > On 30/3/26 22:49, Jason Gunthorpe wrote:
> > > > On Mon, Mar 30, 2026 at 04:47:44PM +1100, Alexey Kardashevskiy wrote:
> > > > 
> > > > > What do I miss? Thanks,
> > > > 
> > > > You can't tell where things start so there is no way to relate the
> > > > offsets to something the kernel can understand.
> > > 
> > > Reported ranges have BAR indexes and start addresses (with the
> > > reported MMIO offset added), and the first reported range starts at
> > > the first 4K of that BAR.
> > 
> > I was told this is not the case, the first reported range can start
> > anywhere in the BAR?
> 
> This is what I am trying to clarify - if all ranges must be reported
> (as some think this is what the PCIe spec says), then no, not
> anywhere.
> 
> pcie r7, Table 11-16 TDI Report Structure, MMIO_RANGE:
> 
> "Each MMIO Range of the TDI is reported with the MMIO reporting offset added."

I think the argument was something like it didn't have to report
non-secure ranges? But I don't know, it was hashed out in some thread
for ARM and then I know our folks looked at it and nobody pushed back
to insist that every single byte of the BAR had to be covered by a
reported range.

I wouldn't take the sentance you quoted as confirmation, you need a
sentance that says every single byte of the BAR is covered by a single
reported range.

Jason