[PATCH v8 9/9] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

Manikanta Maddireddy
2026-03-24T19:11:53Z

Program ASPM L1 entrance latency from the optional aspm-l1-entry-delay-ns
device tree property instead of of_data. Convert the value from nanoseconds
to the hardware encoding (log2(us) + 1, 3-bit field). If the property is
absent, default to 7 (maximum latency).

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V8: Use aspm-l1-entry-delay-ns instead of of_data
Changes V1 -> V7: None

drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 3278353b2c29..a856a48362df 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -18,6 +18,7 @@
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
+#include <linux/log2.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_pci.h>
@@ -272,6 +273,7 @@ struct tegra_pcie_dw {
u32 aspm_cmrt;
u32 aspm_pwr_on_t;
u32 aspm_l0s_enter_lat;
+ u32 aspm_l1_enter_lat;

struct regulator *pex_ctl_supply;
struct regulator *slot_ctl_3v3;
@@ -710,6 +712,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
+ val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
+ val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
val |= PORT_AFR_ENTER_ASPM;
dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
}
@@ -1110,6 +1114,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
{
struct platform_device *pdev = to_platform_device(pcie->dev);
struct device_node *np = pcie->dev->of_node;
+ u32 val;
int ret;

pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
@@ -1136,6 +1141,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
dev_info(pcie->dev,
"Failed to read ASPM L0s Entrance latency: %d\n", ret);

+ /* Default to max latency of 7. */
+ pcie->aspm_l1_enter_lat = 7;
+ ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
+ if (!ret) {
+ u32 us = max(val / 1000, 1U);
+
+ pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7U);
+ }
+
ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
if (ret < 0) {
dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
--
2.34.1