[PATCH v8 7/9] PCI: tegra194: Add core monitor clock support

Manikanta Maddireddy
2026-03-24T19:11:42Z

From: Vidya Sagar <vidyas@nvidia.com>

Add support for Tegra PCIe core clock monitoring. Monitoring tracks rate
changes that may occur due to link speed changes and is useful for
detecting core clock changes not initiated by software. Parse the monitor
clock from device tree and enable it when present.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V8: Fix commit message
Changes V1 -> V7: None

drivers/pci/controller/dwc/pcie-tegra194.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 4527d4759e42..3278353b2c29 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -249,6 +249,7 @@ struct tegra_pcie_dw {
struct resource *atu_dma_res;
void __iomem *appl_base;
struct clk *core_clk;
+ struct clk *core_clk_m;
struct reset_control *core_apb_rst;
struct reset_control *core_rst;
struct dw_pcie pci;
@@ -945,6 +946,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
}

clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
+ if (clk_prepare_enable(pcie->core_clk_m))
+ dev_err(pci->dev, "Failed to enable core monitor clock\n");

return 0;
}
@@ -1017,6 +1020,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
val &= ~PCI_DLF_EXCHANGE_ENABLE;
dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);

+ /*
+ * core_clk_m is enabled as part of host_init callback in
+ * dw_pcie_host_init(). Disable the clock since below
+ * tegra_pcie_dw_host_init() will enable it again.
+ */
+ clk_disable_unprepare(pcie->core_clk_m);
tegra_pcie_dw_host_init(pp);
dw_pcie_setup_rc(pp);

@@ -1610,6 +1619,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)

static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
{
+ clk_disable_unprepare(pcie->core_clk_m);
dw_pcie_host_deinit(&pcie->pci.pp);
tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
@@ -2160,6 +2170,11 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
return PTR_ERR(pcie->core_clk);
}

+ pcie->core_clk_m = devm_clk_get_optional(dev, "core_m");
+ if (IS_ERR(pcie->core_clk_m))
+ return dev_err_probe(dev, PTR_ERR(pcie->core_clk_m),
+ "Failed to get monitor clock\n");
+
pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"appl");
if (!pcie->appl_res) {
@@ -2356,6 +2371,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
if (!pcie->link_state)
return 0;

+ clk_disable_unprepare(pcie->core_clk_m);
tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);

--
2.34.1