[PATCH v8 2/9] PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode

Manikanta Maddireddy
2026-03-24T19:10:59Z

From: Vidya Sagar <vidyas@nvidia.com>

Calibrate 'pipe to universal PHY(UPHY)' (P2U) for the Endpoint controller
to request UPHY PLL rate change to Gen1 during initialization. This helps
to reset stale PLL state from the previous bad link state.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes v8: Fix commit message
Changes V1 -> V7: None

drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index c823285368f5..37fcac55838f 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1071,6 +1071,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
ret = phy_power_on(pcie->phys[i]);
if (ret < 0)
goto phy_exit;
+
+ if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+ phy_calibrate(pcie->phys[i]);
}

return 0;
--
2.34.1