* [PATCH 0/2] PCI: mediatek-gen3: Fix the control timing of PERST#
@ 2026-04-13 7:13 Jian Yang
2026-04-13 7:13 ` [PATCH 1/2] PCI: mediatek-gen3: Fix PERST# control timing during system startup Jian Yang
2026-04-13 7:13 ` [PATCH 2/2] PCI: mediatek-gen3: Add a shutdown callback to cotnrol PERST# signal Jian Yang
0 siblings, 2 replies; 3+ messages in thread
From: Jian Yang @ 2026-04-13 7:13 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Ryder Lee,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas
Cc: linux-pci, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, jian.yang, chuanjia.liu,
yonglong.wu
Dear maintainers,
The purpose of this patch series is to fix the PERST# control timing
in the MediaTek PCIe Gen3 controller driver so that it complies with
the PCIe CEM specification.
In the current MediaTek PCIe Gen3 controller driver, there are two
issues with PERST# timing:
1. During the power-up phase (i.e., before PCIe link-up), on some
MediaTek SoCs PERST# is de-asserted before the REFCLK becomes stable;
2. During system shutdown, PERST# is not asserted before power is
removed.
Patch 1 fixes the reset signal sequencing during the power-up phase.
Patch 2 adds a shutdown callback to control PERST# during system
shutdown.
Best regards,
Jian Yang
Jian Yang (2):
PCI: mediatek-gen3: Fix PERST# control sequence at system startup
phase
PCI: mediatek-gen3: Add shutdown callback to cotnrol PERST# signal
drivers/pci/controller/pcie-mediatek-gen3.c | 30 ++++++++++++++++++---
1 file changed, 27 insertions(+), 3 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/2] PCI: mediatek-gen3: Fix PERST# control timing during system startup
2026-04-13 7:13 [PATCH 0/2] PCI: mediatek-gen3: Fix the control timing of PERST# Jian Yang
@ 2026-04-13 7:13 ` Jian Yang
2026-04-13 7:13 ` [PATCH 2/2] PCI: mediatek-gen3: Add a shutdown callback to cotnrol PERST# signal Jian Yang
1 sibling, 0 replies; 3+ messages in thread
From: Jian Yang @ 2026-04-13 7:13 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Ryder Lee,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas
Cc: linux-pci, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, jian.yang, chuanjia.liu,
yonglong.wu
Some of MediaTek's chip will stop generating REFCLK if the
PCIE_PHY_RSTB signal of PCIe controller is asserted.
We have to adjust the control timing as follows to ensure that PERST#
will be de-asserted after the REFCLK is stable:
Assert all reset signals -> delay 10ms -> De-assert all reset signals
except PERST# -> delay 100ms -> De-assert PERST#
Signed-off-by: Jian Yang <jian.yang@mediatek.com>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 25 ++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index b0accd828589..58ba1aa35a22 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -62,6 +62,11 @@
#define PCIE_PHY_RSTB BIT(1)
#define PCIE_BRG_RSTB BIT(2)
#define PCIE_PE_RSTB BIT(3)
+/*
+ * Described in the datasheet of MediaTek PCIe Gen3 controller.
+ * After set PCIE_BRG_RSTB, wait 10ms before accessing PCIe internal registers.
+ */
+#define PCIE_BRG_RST_RDY_MS 10
#define PCIE_LTSSM_STATUS_REG 0x150
#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
@@ -430,6 +435,21 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie)
return err;
}
+ /*
+ * Some of MediaTek's chips won't output REFCLK when PCIE_PHY_RSTB is
+ * asserted, we have to de-assert MAC & PHY & BRG reset signals first
+ * to allow the REFCLK to be stable. While PCIE_BRG_RSTB is asserted,
+ * there is a short period during which the PCIe internal register
+ * cannot be accessed, so we need to wait 10ms here.
+ */
+ msleep(PCIE_BRG_RST_RDY_MS);
+
+ if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
+ /* De-assert MAC, PHY and BRG reset signals */
+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+ }
+
/*
* Described in PCIe CEM specification revision 6.0.
*
@@ -439,9 +459,8 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie)
msleep(PCIE_T_PVPERL_MS);
if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
- /* De-assert reset signals */
- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
- PCIE_PE_RSTB);
+ /* De-assert PERST# signal */
+ val &= ~PCIE_PE_RSTB;
writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] PCI: mediatek-gen3: Add a shutdown callback to cotnrol PERST# signal
2026-04-13 7:13 [PATCH 0/2] PCI: mediatek-gen3: Fix the control timing of PERST# Jian Yang
2026-04-13 7:13 ` [PATCH 1/2] PCI: mediatek-gen3: Fix PERST# control timing during system startup Jian Yang
@ 2026-04-13 7:13 ` Jian Yang
1 sibling, 0 replies; 3+ messages in thread
From: Jian Yang @ 2026-04-13 7:13 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Ryder Lee,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas
Cc: linux-pci, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, jian.yang, chuanjia.liu,
yonglong.wu
Add a shutdown callback to control the timing of PERST# and power
during system shutdown, ensuring that the PERST#, as required by the
PCIe CEM specification, is active before the power on connector is
removed.
Signed-off-by: Jian Yang <jian.yang@mediatek.com>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 58ba1aa35a22..4915979968b9 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -1285,6 +1285,14 @@ static void mtk_pcie_remove(struct platform_device *pdev)
mtk_pcie_irq_teardown(pcie);
}
+static void mtk_pcie_shutdown(struct platform_device *pdev)
+{
+ struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev);
+
+ mtk_pcie_devices_power_down(pcie);
+ mtk_pcie_power_down(pcie);
+}
+
static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie)
{
int i;
@@ -1423,6 +1431,7 @@ MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
static struct platform_driver mtk_pcie_driver = {
.probe = mtk_pcie_probe,
.remove = mtk_pcie_remove,
+ .shutdown = mtk_pcie_shutdown,
.driver = {
.name = "mtk-pcie-gen3",
.of_match_table = mtk_pcie_of_match,
--
2.45.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2026-04-13 7:13 [PATCH 0/2] PCI: mediatek-gen3: Fix the control timing of PERST# Jian Yang
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