From: Bjorn Helgaas <helgaas@kernel.org>
To: Hans Zhang <18255117159@163.com>, t@bhelgaas
Cc: sashiko@lists.linux.dev, linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: cadence: Use cdns_pcie_find_capability() to get PCIe Cap offset in host driver
Date: Wed, 6 May 2026 12:12:27 -0500 [thread overview]
Message-ID: <20260506171227.GA797577@bhelgaas> (raw)
In-Reply-To: <505b1138-b4a7-4519-b6e5-5da6e06d615d@163.com>
On Thu, May 07, 2026 at 12:04:34AM +0800, Hans Zhang wrote:
> On 5/6/26 05:23, Bjorn Helgaas wrote:
> > On Mon, May 04, 2026 at 04:22:26PM +0800, Hans Zhang wrote:
> > > On 5/4/26 00:52, sashiko-bot@kernel.org wrote:
> > > > Thank you for your contribution! Sashiko AI review found 1
> > > > potential issue(s) to consider:
> > > >
> > > > - [Critical] cdns_pcie_find_capability() searches the wrong
> > > > register space in Host mode and its return value is not validated,
> > > > leading to Root Port configuration space corruption.
> > > > --
> > > >
> > > > commit 09b3c64b8f5892eb365acd13030a8067652a15e8
> > > > Author: Hans Zhang <18255117159@163.com>
> > > >
> > > > PCI: cadence: Use cdns_pcie_find_capability() to get PCIe Cap offset in host driver
> > > >
> > > > This commit replaces the hardcoded CDNS_PCIE_RP_CAP_OFFSET with a dynamic
> > > > lookup using cdns_pcie_find_capability() in Cadence PCIe host-related
> > > > functions. The goal is to ensure correct operation across various SoC designs
> > > > where the capability might not reside at offset 0xC0.
> > > >
> > > > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> > > > > index 2b0211870f02..5013d3fe23b5 100644
> > > > > --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> > > > > +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> > > > > @@ -26,14 +26,14 @@ EXPORT_SYMBOL_GPL(bar_max_size);
> > > > > int cdns_pcie_host_training_complete(struct cdns_pcie *pcie)
> > > > > {
> > > > > - u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
> > > > > unsigned long end_jiffies;
> > > > > u16 lnk_stat;
> > > > > + u8 cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP);
> > > >
> > > > Does this capability search scan the correct register space when
> > > > operating in host mode?
> > > >
> > > > Looking at the helper function, it uses cdns_pcie_read_cfg() which
> > > > reads directly from the base address without the Root Port offset:
> > > >
> > > > drivers/pci/controller/cadence/pcie-cadence.c:cdns_pcie_find_capability() {
> > > > return PCI_FIND_NEXT_CAP(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST,
> > > > cap, NULL, pcie);
> > > > }
> > > >
> > > > However, the Root Port configuration registers are physically
> > > > located at pcie->reg_base + CDNS_PCIE_RP_BASE. Could this cause
> > > > the search to scan the Local Management register space instead,
> > > > failing to find PCI_CAP_ID_EXP and returning 0?
> > >
> > > I don't think we need to worry about this issue.
> > >
> > > As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions
> > > are required to implement the PCI Express Capability structure,
> > > which must be included somewhere in this linked list;
> > >
> > > So, it won't return 0 here.
> >
> > It's true that all Root Ports must have a PCIe Capability, but
> > that's not related to this issue.
> >
> > cdns_pcie_host_init_root_port() accesses PCI_EXP_LNKCAP at the
> > address:
> >
> > pcie->reg_base + CDNS_PCIE_RP_BASE + CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP
> >
> > but when we search with cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP),
> > we start reading at:
> >
> > pcie->reg_base + PCI_CAPABILITY_LIST
> >
> > It should be starting at:
> >
> > pcie->reg_base + CDNS_PCIE_RP_BASE + PCI_CAPABILITY_LIST
> >
> > Previously, cdns_pcie_find_capability() and
> > cdns_pcie_find_ext_capability() were only used for endpoints, and I
> > assume they work fine there. There is pcie->is_rc, so there should be
> > a way to make this work for both endpoints and Root Ports.
>
> The reason for using the "is_rc" tag is that for Cadence IP, it is not only
> applicable to the RC or EP mode, but also there are significant differences
> between the LGA and HPA generations of IP. Including register offset values,
> definitions, etc., it fails to achieve good compatibility. It is not like
> Synopsys IP, where compatibility has been handled very well. It was truly
> out of necessity.
I think cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP) fails on Root
Ports because it doesn't include the CDNS_PCIE_RP_BASE offset. Do you
have hardware where you can test that?
next prev parent reply other threads:[~2026-05-06 17:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-03 16:19 [PATCH] PCI: cadence: Use cdns_pcie_find_capability() to get PCIe Cap offset in host driver Hans Zhang
2026-05-03 16:52 ` sashiko-bot
2026-05-04 8:22 ` Hans Zhang
2026-05-05 21:23 ` Bjorn Helgaas
2026-05-06 16:04 ` Hans Zhang
2026-05-06 17:12 ` Bjorn Helgaas [this message]
2026-05-07 3:31 ` Hans Zhang
2026-05-07 3:48 ` Hans Zhang
2026-05-07 12:31 ` Aksh Garg
2026-05-07 15:21 ` Hans Zhang
2026-05-07 15:32 ` Bjorn Helgaas
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